FAN2558 Datasheet, PDF(2/12 Page) Fairchild Semiconductor

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FAN2558 Datasheet, PDF (2/12 Pages) Fairchild Semiconductor – 180mA Low Voltage CMOS LDO

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VCC

CLK0

VCC

CLK1

CLK_SEL

24 23 22 21 20 19 18 17

VCCO

VCC0

MC100ES8111

VCCO

12345678

Figure 1. MC100ES8111 Logic Diagram

Figure 2. 23-Lead Package Pinout (Top View)

Table 1. Pin Configuration(1)

CLK0, CLK0

CLK1, CLK1

I/O

Input

Type

HSTL

PECL

Function

Differential HSTL reference clock signal input

Differential PECL reference clock signal input

CLK_SEL

Q[0-9], Q[0-9]

Input

Output

LVCMOS

HSTL

Reference clock input select

Output enable/disable. OE is synchronous to tlhe input reference clock which

eliminates possible output runt pulses when the OE state is changed.

Differential clock outputs

GND

VCC

VCCO

Supply

Negative power supply

Positive power supply of the device core (3.3 V)

Positive power supply of the HSTL outputs. All VCCO pins must be connected to the

positive power supply (1.5 V or 1.8 V) for correct DC and AC operation.

1. Input pull-up/pull-down resistors have a value of 75 kâ¦.

Table 2. Function Table

Control

CLK_SEL

Default

CLK0, CLK0 (HSTL) is the active differential clock CLK1, CLK1 (PECL) is the active differential clock

input

Q[0-9], Q[0-9] are active. Deassertion of OE can be Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of

asynchronous to the reference clock without

OE can be asynchronous to the reference clock

generation of output runt pulses.

without generation of output runt pulses.

MC100ES8111

Freescale Confidential Proprietary

NDA Required / Preliminary

Advanced Clock Drivers Device Data

Freescale Semiconductor

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