FAN2558 Datasheet, PDF (5/12 Pages) Fairchild Semiconductor – 180mA Low Voltage CMOS LDO

Table 6. AC Characteristics (V_CC = 3.3 V ± 5%, V_CCO = 1.5 V ± 0.1 V or V_CCO = 1.8 V ± 0.1 V), T_J = 0°C to +110°C⁽¹⁾
Symbol Characteristics
Min
Typ
Max
Unit
Condition
REF_SEL= 0, Active Clock Input Pair CLK0, CLK0 (HSTL differential signals)
V_DIF
V_{X, IN}
Differential Input Voltage⁽²⁾ (Peak-to-Peak)
Differential Cross Point Voltage⁽³⁾
0.4
0.68
f_CLK Input Frequency
0
t_PD Propagation Delay CLK0 to Qn
V_CCO = 1.8 V
700
V_CCO = 1.5 V
700
t_SK(PP) Output-to-Output Skew (Part-to-Part)
t_SK(P) Output Pulse Skew⁽⁴⁾
V_CCO = 1.8 V
V_CCO = 1.5 V
V_CCO = 1.8 V
V_CCO = 1.5 V
REF_SEL = 1, Active Clock Input Pair CLK1, CLK1 (PECL differential signals)
V_PP Differential Input Voltage⁽⁵⁾ (Peak-to-Peak)
0.2
V_CMR Differential Input Crosspoint Voltage⁽⁶⁾
1.0
f_CLK Input Frequency
0
t_PD Propagation Delay CLK1 to Qn
V_CCO = 1.8 V
590
V_CCO = 1.5 V
590
t_SK(PP) Output-to-Output Skew (Part-to-Part)
t_SK(P) Output Pulse Skew⁽⁷⁾
V_CCO = 1.8 V
V_CCO = 1.5 V
V_CCO = 1.8 V
V_CCO = 1.5 V
HSTL Clock Outputs (Qn, Qn)
990
1030
860
910
0.9
625
1270
1420
570
720
100
150
V
V
MHz
ps
ps
ps
ps
ps
ps
Differential
Differential
1.0
V_CC-0.6
625
1220
1360
630
770
150
200
V
V
MHz
ps
ps
ps
ps
ps
ps
Differential
Differential
Differential
V_{X, OUT}
V_OH
V_OL
V_O(P-P)
t_SK(O)
t_JIT(CC)
t_r, t_f
t_PDL(8)
t_PLE(9)
Output Differential Crosspoint
Output High Voltage
Output Low Voltage
V_CCO = 1.8 V
V_CCO = 1.5 V
Differential Output Voltage (Peak-to-Peak) V_CCO = 1.8 V
V_CCO = 1.5 V
Output-to-Output Skew
V_CCO = 1.8 V
V_CCO = 1.5 V
Output Cycle-to-Cycle Jitter RMS (1 σ)
Output Rise/Fall Time
Output Disable Time
Output Enable Time
0.68
V_CCO-0.8 V
V_CCO-0.5 V
0.2
0.45
0.40
150
2.5·T + t_PD
3.0·T + t_PD
0.91
37
60
1.1
1.5
1.5
0.8
1.0
1.0
80
105
1.0
800
3.5·T + t_PD
4.0·T + t_PD
V
V
V
V
V
V
ps
Differential
ps
ps
ps 20% to 80%
ns T=CLKn period
ns T=CLKn period
1. AC characteristics apply for parallel output termination of 50 Ω to V_TT (GND).
2. V_DIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.
3. V_X (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V_X (DC)
range and the input swing lies within the V_DIF (DC) specification.
4. Output duty cycle is DC = (0.5 ± 150 ps · f_OUT) · 100%. E.g. the DC range at f_OUT = 100 MHz is 48.5% < DC < 51.5%.
5. V_PP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device
skew.
6. V_CMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V_CMR
(AC) range and the input swing lies within the V_PP (AC) specification. Violation of V_CMR (AC) or V_PP (AC) impacts the device propagation
delay, device and part-to-part skew.
7. Output pulse skew is the absolute difference of the propagation delay times: | t_PLH - t_PHL |. The output duty cycle is DC = (0.5 ± 200 ps ·
f_OUT) · 100%. E.g. the DC range at f_OUT = 100 MHz and V_CCO = 1.5 V is 48.0% < DC < 52.0%.
8. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
9. Propagation delay OE assertion to output enabled (active).
Advanced Clock Drivers Device Data
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MC100ES8111
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