MIC7400_15 Datasheet, PDF (47/68 Pages) Micrel Semiconductor – Configurable PMIC, Five-Channel Buck Regulator Plus One-Boost with HyperLight Load® and I2C Control

Micrel, Inc.
MIC7400
Appendix A
I²C Control Register
The MIC7400 I²C Read/Write registers are detailed here. During normal operation, the configuration data can be saved
into non-volatile registers in EEPROM by addressing the chip and writing to SAVECONFIG key = 66’h. Saving CONFIG
data to EEPROM takes time so the external host should poll the MIC7400 and read the CONFIG bit[1] of EEPROM Ready
register 01’h to determine the end of programming.
All transactions start with a control byte sent from the I²C master device. The control byte begins with a START condition,
followed by a 7-bit slave address. The slave address is seven bits long followed by an eighth bit which is a data direction
bit (R/W), a “0” indicates a transmission (WRITE) and a “1” indicates a request for data (READ). A data transfer is always
terminated by a STOP condition that is generated by the master.
Serial Port Operation
External Host Interface
Bidirectional I²C port capable of Standard (up to 100kbits/s), Fast (up to 400kbits/s), Fast Plus (up to 1Mbit/s) and High
Speed (up to 3.4Mbit/s) as defined in the I²C-Bus Specification.
The MIC7400 acts as an I²C slave when addressed by the external host. The MIC7400 slave address uses a fixed 7-bit
code and is followed by an R/W bit which is part of the control word that is right after the start bit as shown in Figure 22 in
the Device Address column.
The MIC7400 can receive multiple data bytes after a single address byte and automatically increments its register pointer
to block fill internal volatile memory. Byte data is latched after individual bytes are received so multi-byte transfers could
be corrupted if interrupted mid-stream.
No system clock is required by the digital core for I²C access from the external host (only the host SCL clock is assumed).
In order to prevent spurious operation of the I²C, if a start bit is seen, then any partial communication is aborted and new
I²C data is allowed. Start bit is when SDA goes low when SCL is high. Stop bit is when SDA goes high when SCL is high.
Normal I²C exchange is shown in Figure 22.
March 3, 2015
Figure 22. Read/Write Protocol
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Revision 2.0