MIC7400_15 Datasheet, PDF (29/68 Pages) Micrel Semiconductor – Configurable PMIC, Five-Channel Buck Regulator Plus One-Boost with HyperLight Load® and I2C Control

Micrel, Inc.
During start-up sequencing if Output 1 is still shorted,
Outputs 2 through 4 will come up normally. Once an
overcurrent condition is sensed, then the fault register is
set to “1” and the start-up sequence will stop and no
further outputs will be enabled. See Figure 9 for default
start-up sequence.
Boost Current Limit
The boost current limit features cycle-by-cycle protection.
The duty cycle is cut immediately once the current limit is
hit. When the boost current limit is hit for five consecutive
cycles, the FAULT signal is asserted and remains
asserted with the boost converter keeping on running
until the boost is powered off.
This protects the boost in normal overload conditions, but
not in a short-to-ground case. For a short circuit to
ground, the boost current limit will not be able to limit the
inductor current. This short-circuit condition is sensed by
the current in the disconnect switch. When the disconnect
switch current limit is hit for four consecutive master clock
cycles (2MHz), regardless if the boost is switching or not,
both the disconnect switch and boost are latched off
automatically and the FAULT signal is asserted.
The output can be turned back on by recycling the input
power or by software control. To clear the overcurrent
fault by software control, set the enable register bit to “0”
then clear the overcurrent fault by setting the fault
register bit to “0”.
Global Power Good Pin
The global power-good output indicates that all the
outputs are above the 91% limit after the power-up
sequence is completed. Once the power-up sequence is
complete, the global power good output stays high unless
an output falls below its power-good limit, a thermal fault
occurs, the input voltage drops below the lower UVLO
threshold or an output is turned OFF by setting the
enable register bit to “0” unless the PGOOD_MASK[x] bit
is set to “1” (Default).
A power-good mask bit can be used to control the global
power good output. The power-good mask feature is
programmed through the PGOOD_MASK[x] registers and
is used to ignore an individual power-good fault. When
masked, PGOOD_MASK[x] bit is set to “1”, an individual
power good fault will not cause the global power good
output to de-assert.
If all the PGOOD_MASK[x] bits are set to “1”, then the
power good output de-asserts as soon as the first output
starts to rise. The PGOOD_MASK[x] bit of the last output
must be set to “0” to have the PG output stay low until the
last output reaches 91% of its final value.
The global power-good output is an open-drain output. A
pull-up resistor can be connected to V_IN or V_OUT. Do not
connect the pull-up resistor to a voltage higher than AV_IN.
MIC7400
Standard Delay
There is a programmable timer that is used to set the
standard delay time between each time slot. The timer
starts as soon as the previous time slot’s output power
good goes high. When the delay completes, the
regulators assigned to that time slot are enabled, see
Figure 8.
Figure 8. Standard Delay Time
Power-Up Sequencing
When power is first applied to the MIC7400, all I²C
registers are loaded with their default values from the
EEPROM. There is about a 1.5ms delay before the first
regulator is enabled while the MIC7400 goes through the
initialization process. The DELAY register’s STDEL bits
set the delay between powering up each regulator at
initial power up.
The sequencing registers allow the outputs to come up in
any order. There are six time slots that an output can be
configured to power up in. Each time slot can be
programmed for up to six regulators to be turned on at
once or none at all.
Figure 9 shows an example of this feature. V_OUT4 is
enabled in time slot 1. After a 1ms delay, V_OUT2 and V_OUT3
are enable at the same time in time slot 2. The 1ms is the
standard delay for all of the outputs and can be
programmed from 0ms to 7ms in 1ms. Next, V_OUT1 is
powered up in time slot 3 and V_OUT5 in time slot 4. There
are no regulators programmed for time slot 5. Finally,
V_OUT6 is powered up in time slot 6. The global power good
output, V_PG, goes high as soon as the last output reaches
91% of its final value.
March 3, 2015
29
Revision 2.0