MIC2592B Datasheet, PDF (25/31 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2592B
Status Register Slot B (STATB)
8-Bits, Read-Only
Status Register, Slot B (STATB)
D[7]
D[6]
D[5]
D[4]
D[3]
read-only
read-only
read-only
read/write
read-only
FAULTB
MAINB
VAUXB
VAUXBF
Reserved
D[2]
read/write
12VBF
Micrel
D[1]
read-only
Reserved
D[0]
read/write
3VBF
Bit(s)
FAULTB
Function
FAULT Pin Status - Slot B
MAINB MAIN Enable Status - Slot B
VAUXB VAUX Enable Status - Slot B
VAUXBF
D[3]
12VBF
D[1]
3VBF
Overcurrent Fault: VAUXB supply
Reserved
Overcurrent Fault: +12V supply
Reserved
Overcurrent Fault: 3.3V supply
Operation
1 = Fault pin asserted
(/FAULTB pin is LOW)
0 = Fault pin deasserted
(/FAULTB pin is HIGH)
See Notes 1, 2, and 3.
Represents the actual state (on/off) of the
four Main Power outputs for Slot B
(+12V and +3.3V)
1 = MAIN Power ON
0 = MAIN Power OFF
Represents the actual state (on/off) of the
Auxiliary Power output for Slot B
1 = AUX Power ON
0 = AUX Power OFF
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
Power-Up Default Value:
Command_Byte Value (R/W):
0000 0000b = 00h
0000 0101b = 05h
The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an
overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The
status of the /FAULTB pin is not affected by reading the Status Register or by clearing active status bits.
Notes:
1. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB.
If FAULTB has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to reset
FAULTB.
2. Neither the FAULTB bits nor the /FAULTB pins are active when the MIC2592B power paths are controlled by the System Management Interface.
When using SMI power path control, the AUXENB and ONB pins for that slot must be tied to GND.
3:. If /FORCE_ONB is asserted (low), the /FAULTB pin will be unconditionally forced to its open-drain state. Note, though, that the value in the FAULTB
March 2005
25
M9999-033105