MIC2592B Datasheet, PDF (23/31 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2592B
Control Register, Slot B (CNTRLB)
8-Bits, Read/Write
Control Register, Slot B (CNTRLB)
D[7]
D[6]
D[5]
D[4]
D[3]
read-only
read-only
read only
read only
read-only
AUXBPG
MAINBPG Reserved
Reserved
Reserved
D[2]
read/write
/FORCE_B
ENABLE
D[1]
read/write
MAINB
Micrel
D[0]
read/write
VAUXB
Bit(s)
Function
AUXBPG AUX output power-good status, Slot B
MAINBPG MAIN output power-good status, Slot B
D[5]
Reserved
D[4]
Reserved
D[3]
Reserved
/FORCE_B Allows or inhibits the operation of the /FORCE_ONB
ENABLE input pin
MAINB MAIN enable control, Slot B
VAUXB VAUX enable control, Slot B
Operation
1 = Power-is-Good
(VAUXB Output is above its UVLO threshold)
1 = Power-is-Good
(MAINB Outputs are above their UVLO
thresholds)
Always read as zero
Always read as zero
Always read as zero
0 = /FORCE_ONB is enabled
1 = /FORCE_ONB is disabled
0 = Off, 1 = On
0 = Off, 1 = On
Power-Up Default Value:
Command_Byte Value (R/W):
0000 0000b = 00h
0000 0011b = 03h
The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.
Notes:
1. The state of the /PWRGDB pin is the logical AND of the values of the AUXBPG and the MAINBPG bits, except when /FORCE_ONB is asserted. If
/FORCE_ONB is asserted (the pin is pulled low), and /FORCE_BENABLE is set to a logic zero, the /PWRGDB pin will be unconditionally forced to
its open-drain (“Power Not Good”) state.
March 2005
23
M9999-033105