MIC2592B Datasheet, PDF (19/31 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2592B
Micrel
Thermal Shutdown
The internal VAUX[A/B] MOSFETs are protected against
damage not only by current limiting, but by dual-mode
overtemperature protection as well. Each slot controller on
the MIC2592B is thermally isolated from the other. Should
an overcurrent condition raise the junction temperature of
one slot’s controller and pass elements to 140°C, all of the
outputs for that slot (including VAUX) will be shut off and
the slot’s /FAULT output will be asserted. The other slot’s
operating condition will remain unaffected. However, should
the MIC2592B’s die temperature exceed 160°C, both slots
(all outputs, including VAUXA and VAUXB) will be shut off,
whether or not a current limit condition exists. A 160°C over-
temperature condition additionally sets the overtemperature
bit (OT_INT) in the Common Status Register.
/PWRGD[A/B] Outputs
The MIC2592B has two /PWRGD outputs, one for each slot.
These are open-drain, active-low outputs that require an
external pull-up resistor to V_STBY. Each output is asserted
when a slot has been enabled and has successfully begun
delivering power to its respective +12V, +3.3V, and VAUX
outputs. An equivalent logic diagram for /PWRGD[A/B] is
shown in Figure 8.
/FORCE_ON[A/B] Inputs
These level-sensitive, active-low inputs are provided to
facilitate designing systems using the MIC2592B. Asserting
/FORCE_ON[A/B] will turn on all three of the respective slot’s
outputs (+12V, +3.3V, and VAUX), while specifically defeating
all protections for those outputs. This explicitly includes all
overcurrent and short circuit protections, and on-chip thermal
protection for the VAUX supplies. Additionally, asserting a
slot’s /FORCE_ON[A/B] input will disable all of its input and
output UVLO protections, with the sole exception of that as-
serting either or both of the /FORCE_ON[A/B] inputs will not
disable the VSTBY[A/B] input UVLO.
Asserting /FORCE_ON[A/B] will cause the respective slot’s
/PWRGD[A/B] and /FAULT[A/B] outputs to enter their open-
drain state. Additionally, there are two SMBus accessible
register bits (see CNTRL[A/B] Register Bit D[2]), which can
be set to disable the corresponding slot’s /FORCE_ON[A/B]
pins. This allows system software to prevent these hardware
overrides from being inadvertently activated during normal
use. If not used, each pin should be connected to V_STBY using
an external pull-up resistor. See Figure 6 for details.
General Purpose Input (GPI) Pins
Two pins on the MIC2592B are available for use as GPI
pins. The logic state of each of these pins can be determined
by polling Bits [4:5] of Common Status Register. Both of
these inputs are compliant to 3.3V. If unused, connect each
GPI_[A0/B0] pin to GND.
Hot-Plug Interface (HPI)
Once the input supplies are above their respective UVLO
thresholds, the Hot-Plug Interface can be utilized for power
control by enabling the control input pins (AUXEN[A/B] and
ON[A/B]) for each slot. In order for the MIC2592B to switch
on the VAUX supply for either slot, the AUXEN[A/B] control
must be enabled after the power-on-reset delay, t_POR (typi-
cally, 250µs), has elapsed. The timing response diagram of
Figure 9 illustrates a Hot-Plug Interface operation where an
overcurrent fault is detected by the MIC2592B controller
after initiating a power-up sequence. The MAIN (+12V &
+3.3V) and VAUX[A/B] supply rails, /FAULT, /PWRGD and
/INT output responses for both AUX and MAIN are shown
in the figure.
System Management Interface (SMI)
The MIC2592B’s System Management Interface uses the
Read_Byte and Write_Byte subset of the SMBus protocols
to communicate with its host via the System Management
Interface bus. The /INT output signals the controlling proces-
sor that one or more events need attention, if an interrupt-
driven architecture is used. Note that the MIC2592B does
not participate in the SMBus Alert Response Address (ARA)
portion of the SMBus protocol.
Fault Reporting and Interrupt Generation
SMI-only Control Applications
In applications where the MIC2592B is controlled only by
the SMI, ON[A/B] and AUXEN[A/B] are connected to GND
and the /FORCE_ON[A/B] pins are connected to V_STBY as
shown in Figure 6. In this case, the MIC2592B’s /FAULT[A/B]
outputs and STAT[A/B] Register Bit D[7] (FAULT[A/B])
are not activated as fault status is determined by polling
STAT[A/B] Register Bits D[4], D[2], D[0] and CS (Common
Status) Register Bits D[2:1]. Individual fault bits in STAT[A/B]
and CS registers are asserted after power-on-reset when:
• Either or both CNTRL[A/B] Register Bits D[1:0] are
asserted, AND
• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-
age is lower than its respective ULVO threshold,
OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its filter timeout has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature > 140°C, OR
• The MIC2592B’s global die temperature > 160°C
To clear any one or all STAT[A/B] Register Bits D[4], D[2], D[0]
and/or CS Register Bits D[2], D[1] once asserted, a software
subroutine can perform an “echo reset” where a Logical “1” is
written back to those register bit locations that have indicated
a fault. This method of “echo reset” allows data to be retained
in the STAT[A/B] and/or CS registers until such time as the
system is prepared to operate on that data.
The MIC2592B can operate in interrupt mode or polled mode.
For interrupt-mode operation, the open-drain, active-LOW
/INT output signal is activated after power-on-reset if the
INTMSK bit (CS Register Bit D[3]) has been reset to Logical
“0”. Once activated, the /INT output is asserted by any one
of the fault conditions listed above and deasserted when
one or all STAT[A/B] Register Bits D[4], D[2], D[0] and/or CS
Register Bits D[2], D[1] are reset upon the execution of an
SMBus “echo reset” WRITE_BYTE cycle. For polled-mode
operation, the INTMSK bit should be set to Logical “1,” thereby
inhibiting /INT output pin operation.
For those SMI-control applications where the /FORCE_ON[A/B]
March 2005
19
M9999-033105