MIC28510_12 Datasheet, PDF (17/30 Pages) Micrel Semiconductor – 75V/4A Hyper Speed Control Synchronous DC/DC Buck Regulator

Micrel, Inc.
Internal MOSFET Gate Drive
Figure 1 (the block diagram) shows a bootstrap circuit,
consisting of D1 (a Schottky diode is recommended) and
a capacitor connected from the SW pin to the BST pin
(C_BST). This circuit supplies energy to the high–side drive
circuit. Capacitor C_BST is charged, while the low–side
MOSFET is on, and the voltage on the SW pin is
approximately 0V. When the high–side MOSFET driver
is turned on, energy from C_BST is used to turn the
MOSFET on. As the high–side MOSFET turns on, the
voltage on the SW pin increases to approximately V_IN.
Diode D1 is reverse biased and C_BST floats high while
continuing to keep the high–side MOSFET on. The bias
current of the high–side driver is less than 10mA so a
0.1μF to 1μF is sufficient to hold the gate voltage with
minimal droop for the power stroke (high–side switching)
cycle, i.e. ΔBST = 10mA x 4μs/0.1μF = 400mV. When
the low–side MOSFET is turned back on, C_BST is
recharged through D1. A small resistor in series with
C_BST, can be used to slow down the turn–on time of the
high–side N–channel MOSFET.
The drive voltage is derived from the PV_DD supply
voltage. The nominal low–side gate drive voltage is PV_DD
and the nominal high–side gate drive voltage is
approximately PV_DD – V_DIODE, where V_DIODE is the voltage
drop across D1. An approximate 30ns delay between the
high–side and low–side driver transitions is used to
prevent current from simultaneously flowing unimpeded
through both MOSFETs.
MIC28510
March 2012
17
M9999-030912-A