MIC24420 Datasheet, PDF (17/34 Pages) Micrel Semiconductor – 2.5A Dual Output PWM Synchronous Buck Regulator IC

Micrel, Inc.
C _SS
>
C_OUT
⋅V_OUT
I_{S /C}
⋅ I_SS
Where
I_S/C is the short circuit, fold-back current limit.
C_SS is the capacitor connected to EN/DLY pin
I_SS is the EN/DLY pull up current.
Current Limit Resistor
The current limit circuit responds to the peak inductor
current flowing through the low-side FET. Calculating the
current setting resistor R_CS should take into account the
peak inductor current and the blanking delay of
approximately 100ns.
MIC24420/MIC24421
Short Circuit Protection
It is recommended that a fold-back current characteristic
be implemented to protect both external and internal
MOSFETs during short circuit (S/C) events. This can be
achieved by the addition of one additional resistor R_FBK
(R14 & R19 on the evaluation board) from V_OUT to the
CS pin.
Figure 9. Overcurrent waveform
Figure 9 shows the low-side MOSFET current waveform.
Peak current is measured after a small delay. The
equations used to calculate the current limit resistor
value are shown below:
I_PK
= I_OUT
⋅ ^IPP
2
I_OC
=
I_PK
−
V_OUT ⋅ t _DLY
L
R _CS
=
I_OC
⋅ RDS_ON
I_CS
Where:
I_OC is the current limit set point
L = inductor value
t_DLY = Current limit blanking time ~ 100ns
I_CS is the overcurrent pin sense current (200µA nominal)
R_DS(ON) is the on resistance of the low-side MOSFET
Figure 9a. Short Circuit Protection
Current limit will occur at:
I _OC
=
1
R_{DS (ON )}
⋅ _{⎜⎜⎝⎛} I_CS
⋅ R_CS
+ ^{VOUT ⋅ RCS}
R_FBK
− V_{CS _OFF ⎟⎟⎠⎞}
Where V_{CS_OFF} is the CS comparator offset voltage.
For simplicity, assuming V_{CS_OFF} is 0V, we can set I_S/C
(current limit when V_OUT = 0V) to be half I_OC (current limit
when V_OUT = nominal):
R_CS
=
I_OC ⋅ R_{DS (ON )}
I_CS ⋅ 2
R_FBK
= ^VOUT
I _CS
To determine worst case values, one must take into
account V_CS offset voltage, I_CS range and the range of
values for R_DS(ON) over the operating temperature range.
Some typical example values for a 30mΩ MOSFET:
V_OUT
I_OC
I_S/C R_CS
3.3A 1.7 249
5
4.3A 1.7 249
R_FBK
24.9k
16k
3.3A 1.7 249
3.3
4.3A 1.7 249
16.5k
10.5k
3.3A 1.7 249
1.2
4.3A 1.7 249
5.1k
3.83k
Due to the leading edge blanking, a 100ns slew rate for
the CS pin can be applied without interfering with current
limit operation. Limiting the CS pin’s slew rate will help to
prevent false triggering. A C·R product of at least 20ns
should be used.
June 2012
17
M9999-062012-C