MIC24420 Datasheet, PDF (12/34 Pages) Micrel Semiconductor – 2.5A Dual Output PWM Synchronous Buck Regulator IC

Micrel, Inc.
Soft-start
Enable and soft-start waveforms are shown in Figure 2.
MIC24420/MIC24421
can be connected to another regulator’s EN/DLY pin for
sequencing of the outputs. A pull-up resistor is not used
when the power good pin is connected to another
regulators EN/DLY pin.
Output Sequencing
Sequencing of the outputs can be easily implemented as
shown in Figure 3. The power good pin is used to
disable V_OUT2 until the V_OUT1 reaches regulation.
Sequencing waveforms are shown in Figure 4.
Figure 2. Soft-start Timing Diagram
A capacitor, C_SS, is connected to the EN/DLY pin. The
C_SS capacitor range is 4.7nF to 22nF. Releasing the pin
allows an internal current source to charge the capacitor.
The delay (t_D) between the EN/DLY pin release and
when V_OUT starts to rise can be calculated by the
equation below.
t_D
=
C _SS
× V_{Threshold_Start}
I_SS
Where:
C_SS is the soft-start capacitor.
I_SS is the internal soft-start current (7µA nominal).
V_{Threshold_start} is the EN/DLY pin voltage where the output
starts to rise (1.35V nominal).
The output voltage starts to rise when voltage on the
EN/DLY pin reaches the start threshold. The output
voltage reaches regulation when the EN/DLY pin voltage
reaches the end threshold. The output voltage rise time
(t_R) can be calculated by the equation below:
t_R
=
C_SS
× (V_{Threshold_End}
I _SS
− V_{Threshold_Start}
)
Where:
V_{Threshold_End} is the EN/DLY pin voltage where the output
reaches regulation (2.4V nominal).
As the MIC24420/MIC24421 uses a fold-back, hiccup
mode current limit, care should be taken to select t_R to
ensure startup. See application information for details.
Power Good
Power good is an open drain signal that asserts when
V_OUT exceed the power good threshold. The circuit
monitors the FB pin. The internal FET is turned on while
the FB voltage is below the FB threshold. When voltage
on the FB in exceeds the FB threshold, the FET is
turned off. A pull-up resistor can be connected to PVDD
or an external source. The external source voltage must
not exceed the maximum rating of the pin. The PG pin
June 2012
12
Figure 3. Output Sequencing
Figure 4. Output Sequencing Waveforms
M9999-062012-C