MIC24420 Datasheet, PDF (11/34 Pages) Micrel Semiconductor – 2.5A Dual Output PWM Synchronous Buck Regulator IC

Micrel, Inc.
Functional Description
The MIC24420/MIC24421 are dual output, synchronous
buck regulators. Output regulation is performed using a
fixed frequency, voltage mode control scheme. The fixed
frequency clock drives the two sections 180° out of
phase, which reduces input ripple current.
Oscillator
An internal oscillator provides a clock signal to each of
the two sides. The clock signals are 180° out of phase
with the other. Each phase is used to generate a ramp
for the PWM comparator and a clock pulse that
terminates the switching cycle. The MIC24420 &
MIC24421 oscillator frequencies are nominally 1MHz
and 500 kHz respectively.
UVLO
The UVLO monitors voltage on the VIN pin. The circuit
controls both regulators (side1 and side2). It disables the
output drivers and discharges the EN/DLY capacitor
when VIN is below the UVLO threshold. As VIN rises
above the threshold, the internal high-side FET drivers
and external low-side drives are enabled and the
EN/DLY pins are released.
A low impedance source should be used to supply input
voltage to the MIC24420/MIC24421. When VIN drops
below the UVLO threshold and the outputs turn off, the
change in input current will cause VIN to rise. The
output voltage will momentarily turn back on if the rise in
VIN is greater than the UVLO hysteresis.
The preferred method is to use the EN/DLY pins, as
shown in Figure 1, for startup and shutdown of the
outputs. This avoids the possibility of glitching during
startup and shutdown. If an external control signal is not
available, the circuit in Figure 1A may be used to set a
higher turn-on and turn-off threshold than the internal
UVLO circuit. Moreover, the hysteresis is adjustable and
can accommodate a wider input source impedance
range. Please refer to the MIC841 datasheet for
additional information on selecting the resistor values.
Regulator/Reference
The internal regulator generates an AVDD pin voltage
that powers the internal analog circuit blocks of the low
level analog and digital sections. The AVDD voltage is
also used by the bandgap to generate a nominal 700mV
for the error amplifier reference. The output undervoltage
and power good circuits use the bandgap for their
references. PVDD powers the high-side MOSFET and
low-side gate drive circuits.
The dropout of the internal regulator causes AVDD to
drop when VIN is below 6V. When operating below 6V,
the AVDD pin must be jumpered to VIN. This bypasses
the internal LDO and prevents AVDD from dropping out.
MIC24420/MIC24421
A 4.7µF ceramic capacitor should be used to decouple
AVDD to ground.
EN/DLY pin
The EN/DLY pins are used to turn on, turn off and soft-
start the outputs. The pins can be controlled with an
open collector or open drain device as shown in Figure
1. It must not be actively driven high or damage will
result. When disabling the output with an external
device, the enable pin turn-off time must be less than
1µs.
Figure 1. Enable and soft-start circuit
Figure 1A. Adjustable UVLO startup circuit
Minimum Output Load when Disabled
When one output is disabled and the other enabled, the
disabled output requires a minimum output load to
prevent its output voltage from rising. Typically a 2kΩ
load on the output will keep the output voltage below
100mV. The output setting voltage divider resistors may
be used for the 2kΩ load if the total resistance is set low
enough. A separate output resistor should be used for
lower output voltages since the voltage divider
resistance becomes impractically low.
June 2012
11
M9999-062012-C