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MIC24420 Datasheet, PDF (14/34 Pages) Micrel Semiconductor – 2.5A Dual Output PWM Synchronous Buck Regulator IC
Micrel, Inc.
The following steps can be taken to lower the gate drive
impedance, minimize the dv/dt induced current and
lower the MOSFET’s susceptibility to the induced glitch:
• Choose a low-side MOSFET with a high
CGS/CGD ratio and a low internal gate resistance.
• Do not put a resistor between the LSD output
and the gate.
• Ensure both the gate drive and return etch are
short, low inductance connections.
• Use a 4.5V VGS rated MOSFET. It’s higher gate
threshold voltage is more immune to glitches
than a 2.5V or 3.3V rated MOSFET. MOSFETs
that are rated for operation at less than 4.5 VGS
should not be used.
• Add a resistor in series with the BST pin. This
will slow down the turn-on time of the high-side
MOSFET while leaving the turn-off time
unaffected.
Pre-biased output protection:
It is desirable in synchronous step down converters such
as MIC24420/MIC24421, to prevent the low-side
MOSFET from switching during startup or short periods
in an idle state, since during these times it is possible
that a voltage exists on the output of the converter. If the
low-side switch is allowed to operate, uncontrolled in this
state, large transient voltages can be created at the
switching nodes by ‘open-loop boost’ operation. To
prevent this unwanted operation, the MIC24420/24421
will gradually increase switching cycles on the low-side
MOSFET in ratio to the soft start ramping waveform. Full
operation of the low-side driver is achieved when the
ramp reaches the soft start end threshold (nominally
2.4V) when output voltage is at its nominal level.
Current Limit
The MIC24420/MIC24421 use the synchronous (low-
side) MOSFET’s RDS(ON) to sense an over-current
condition. The low-side MOSFET is used because it
displays lower parasitic oscillations after switching than
the upper MOSFET. Additionally, reduces false tripping
at lower voltage outputs and narrow duty cycles since
the off-time increases as duty cycle decreases. Figure 7
shows how over-current protection is performed using
the low-side MOSFET.
MIC24420/MIC24421
Figure 7. Over-current Circuit
Inductor current, IL, flows from the lower MOSFET
source to the drain during the off-time, causing the drain
voltage to become negative with respect to ground. This
negative voltage is proportional to the instantaneous
inductor current times the MOSFET RDS(ON). The low-
side MOSFET voltage becomes even more negative as
the output current increases.
The over-current circuit operates by passing a known
fixed current source through a resistor RCS. This sets up
an offset voltage (ICS x RCS) that is compared to the VDS
of the low-side MOSFET. When ISD (source-to-drain
current) x RDS(ON) is equal to this voltage the soft-start
circuit is reset and a hiccup current mode is initiated to
protect the power supply and load from excessive
current during short circuits. Fold back current limiting is
recommended to protect the switch devices during short
circuit faults. For more information on this, see the
application information section.
Current Limit Calculations and Maximum Peak Limit
Proper current limiting requires careful selection of the
inductor value and saturation current. If a short circuit
occurs during the off-time, the overcurrent circuit will
take up to a full cycle to detect the overcurrent once it
exceeds the over-current limit. The worst case occurs if
the output current is 0A and a hard short is applied to the
output. The short circuit causes the output voltage to fall,
which increases the pulse width of the regulator. It may
take 3 or 4 cycles for the current to build up in the
inductor before current limit forces the part into hiccup
mode. The wider pulse width generates a larger peak to
peak inductor current which can saturate the inductor.
For this reason, the minimum inductor values for the
MIC24420/MIC24421 are 10µH/22µH respectively and
the maximum peak current limit set-point is 2.7A. The
saturation current for each of these inductors should be
at least 1.5A higher than the overcurrent limit setting.
June 2012
14
M9999-062012-C