MLX81100_14 Datasheet, PDF (13/19 Pages) Melexis Microelectronic Systems – DC-Motor Controller

MLX81100
DC-Motor Controller
4. Pin Description
Pin name
voltage
range
remarks and description
36
1
1
0
4,31,22,
3,37
5
6
2
40
1
2
1
38
1
1
2
39
1
1
0
33
1
1
0
13,14,16
-21
8
8
0
35
1
1
0
VS
GND
VDD5V
V1V8
RTG
PS
SW[7:0]
CWD
Pwr HV
Pwr HV
Pwr LV
Pwr LV
An HV
Pwr HV
Multifunc
HV
An LV
Battery supply voltage; external protection against reverse
polarity needed
Ground: Digital, Analogue, LIN, Driver, Pads: VSSLIN,
VSSDRV,VSSIO,VSSA,VSSD / (PSUB at TQFP only)
Input from Regulator (5 V),
external blocking capacitors
Regulator output (about 1.8 V),
external blocking capacitors
External regulator transistor control output,
to be connected to VDD5V or external n-type Transistor
Switch-able supply (VS) output voltage, internal clamped
High voltage I/O port with wake-up function, configurable
Watch dog load capacitor
42
5,35,26,20
,43,3,4
46
44
45
39
15,17-19
21-24
41
11
1
1
0
SHNT_L
An LV Shunt measurement connection for ADC
13
26,27
2
2
0
24,29
2
2
0
32
1
1
0
LS1, LS2
HS1, HS2
VDRV
An HV
An HV
An HV
Gate driver for external N-channel MOSFET in low-side
configuration
Gate driver for external N-channel MOSFET in high-side
configuration
Regulator output, internal clamped, for pre-charging of
bootstrap capacitors of the high side gate driver
30,31
28,33
38
23,30
2
2
0 HSBC1,HSBC2 An HV Connection of bootstrap capacitors
27,34
25,28
2
2
0
BRMID1,BRMID2
An HV
Midpoint of a full bridge (usually the source of high-side
FET and drain of it’s low-side FET)
29,32
7
1
1
0
LIN
An HV LIN transceiver BUS pin
9
34
1
1
0
2,8,12,
9,6,1
6
0
6
CLKO
IO[5:0]
Dig 5V
Dig LV
Clock 307kHz for possible external charge pump or Chip
select/input
Digital IO (MelexCM)
40
2,10,14,
11,7,1
10,15
2
0
2
TI[1:0]
Test input Test inputs for Melexis (MelexCM) - connect to GND
12,16
5
1
0
1
TO
Test output Test output for Melexis (MelexCM), unconn. in application
6
IO(0)
40
1
IO(5)
VSSA
VSSLIN
TO
IO(1)
LIN
IO(4)
IO(2)
TI(1)
MLX81100 – Product Abstract
HSBC2
HS2
BRMID2
LS2
LS1
BRMID1
HS1
HSBC1
VSSIO
SW(0)
IO(0)
IO(5)
VSSA
PSUB
VSSLIN
TO
IO(1)
VDD5V
LIN
IO(4)
IO(2)
TI(1)
48
1
QFN40
Page 13 of 19
nc.
VSSDRV
HSBC2
HS2
BRMID2
LS2
LS1
BRMID1
HS1
HSBC1
VSSIO
nc.
TQFP48
June 2012
Rev 021