MG82FX532AE Datasheet, PDF (95/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

15.3. Data Mode
Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit,
CPOL, allows the user to set the clock polarity. The following figures show the different settings of Clock Phase
Bit, CPHA.
Figure 15-5. SPI Slave Transfer Format with CPHA=0
Clock Cycle
1
2
3
4
5
6
7
8
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit in
MOSI
Slave Intput
DORD=0
MSB 6
5
4
3
2
1
DORD=1
LSB 1
2
3
4
5
6
MISO
Slave Output
1st bit out
data sampled
nSS (if SSIG=0)
This edge is used by the slave to shift out the 1st bit
of each data byte while CPHA=0
LSB
MSB
Not
defined
Figure 15-6. Slave Transfer Format with CPHA=1
Clock Cycle
1
2
3
4
5
6
7
8
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit in
MOSI
Slave Intput
DORD=0
MSB 6
5
4
3
2
1
LSB
DORD=1
LSB 1
2
3
4
5
6
MSB
MISO
Slave Output
1st bit out
Not
defined
Not defined data sampled
nSS (if SSIG=0)
MEGAWIN
MG82FE/L532 Data Sheet
95