MG82FX532AE Datasheet, PDF (29/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

7. 8051 CPU Description
7.1. CPU Register
PSW: Program Status Word
SFR Page
= All
SFR Address = 0xD0
RESET = 0000-0000
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CY: Carry bit.
AC: Auxiliary carry bit.
F0: General purpose flag 0.
RS1: Register bank select bit 1.
RS0: Register bank select bit 0.
OV: Overflow flag.
F1: General purpose flag 1.
P: Parity bit.
The program status word (PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown above, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the
―Accumulator‖ for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in the on-chip-data-RAM section.
A number of instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.
SP: Stack Pointer
SFR Page
= All
SFR Address = 0x81
7
6
5
SP[7]
SP[6]
SP[5]
R/W
R/W
R/W
DPL: Data Pointer Low
SFR Page
= All
SFR Address = 0x82
7
6
5
DPL[7]
DPL[6]
DPL[5]
R/W
R/W
R/W
DPH: Data Pointer High
SFR Page
= All
SFR Address = 0x83
7
6
5
DPH[7] DPH[6] DPH[5]
R/W
R/W
R/W
B: B Register
SFR Page
SFR Address
7
B[7]
R/W
= All
= 0xF0
6
5
B[6]
B[5]
R/W
R/W
4
SP[4]
R/W
RESET = 0000-0111
3
2
SP[3]
SP[2]
R/W
R/W
RESET = 0000-0000
4
3
2
DPL[4] DPL[3] DPL[2]
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
DPH[4] DPH[3] DPH[2]
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
B[4]
B[3]
B[2]
R/W
R/W
R/W
1
SP[1]
R/W
1
DPL[1]
R/W
1
DPH[1]
R/W
1
B[1]
R/W
0
SP[0]
R/W
0
DPL[0]
R/W
0
DPH[0]
R/W
0
B[0]
R/W
MEGAWIN
MG82FE/L532 Data Sheet
29