MG82FX532AE Datasheet, PDF (63/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

Transmission is initiated by any instruction that uses SBUF0 as a destination register. The ―write to SBUF0‖
signal triggers the UART0 engine to start the transmission. The data in the SBUF0 would be shifted into the
RXD0(P3.0) pin by each raising edge shift clock on the TXD0(P3.1) pin. After eight raising edge of shift clocks
passing, TI would be asserted by hardware to indicate the end of transmission. Figure 13-4 shows the
29 5H
transmission waveform in Mode 0.
Reception is initiated by the condition REN0=1 and RI0=0. At the next instruction cycle, the Serial Port 0
Controller writes the bits 11111110 to the receive shift register, and in the next clock phase activates Receive.
Receive enables Shift Clock which directly comes from RX Clock to the alternate output function of P3.1 pin.
When Receive is active, the contents on the RXD0(P3.0) pin would be sampled and shifted into shift register by
falling edge of shift clock. After eight falling edge of shift clock, RI0 would be asserted by hardware to indicate the
end of reception. Figure 13-5 shows the reception waveform in Mode 0.
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Figure 12-3 Serial Port 0 Mode 0
SYSCLK
¸2
“0”
¸ 12
“1”
URM0X6
80C51 Internal BUS
Write
SBUF
TX Clock
RX Clock
TXBUF
RXD Alternated
for Input/output
Function
REN
RI
RXSTART
UART engine
TI
RI
RXBUF
Shift-clock
TXD Alternated
for output
Function
Serial Port Interrupt
Read
SBUF
80C51 Internal BUS
MEGAWIN
MG82FE/L532 Data Sheet
63