MG82FX532AE Datasheet, PDF (138/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

1: Enable internal low frequency RC oscillator. If this bit is set by CPU software, it needs 50us to have stable
output after IHRCOE is enabled.
Bit 1~0: OSC input selection.
OSCS[1:0]
00
01
10
11
OSCin Source
IHRCO (Default)
ILRCO
External Clock Input
Ext. Crystal Oscillating
P6.0 Function
P6.0 or IHRCO output
P6.0
Clock Input
XTAL2
P6.1 Function
P6.1
P6.1
P6.1
XTAL1
AUXRB: Auxiliary Register B
SFR Address = IFMT
RESET = xxx0-00x0
7
6
5
4
3
2
1
0
--
--
--
IAPO
LPM3
LPM2
--
LPM0
R
R
R
R/W
R/W
R/W
R
R/W
Bit 7~5: Reserved. Software must write ―0‖ on these bits when AUXRB is written.
Bit 4: IAPO, IAP function Only.
0: Maintain IAP region to service IAP function and code execution when the flash region lower than AP boundary
defined by IAPLB.
1: Disable the code execution in IAP region and the region only service IAP function.
Bit 3, 2, 0: LPM3, 2, 0. Control bits for Low power mode operation.
If the frequency of OSCin and SYSCLK is slower than 6MHz, software can write ―1‖s on this bits to reduce
operating current. Otherwise, software must write ―0‖s on this bit to maintain the high speed performance. Other
values writing on these bits are not permitted.
Bit 1: Reserved. Software must write ―0‖ on this bit when AUXRB is written.
138
MG82FE/L532 Data Sheet
MEGAWIN