MG82FX564AE Datasheet, PDF (46/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

IP0L, IP0H, EIP1L and EIP1H are combined to 4-level priority interrupt as the following table.
{IPH.x , IPL.x}
11
10
01
00
Priority Level
1 (highest)
2
3
4
There are 14 interrupt sources available in MG82Fx564. Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the SFRs named IE, EIE1, and XICON. This register also contains a global
disable bit(EA), which can be cleared to disable all interrupts at once.
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPxH and
the other in IPxL register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two
interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine
which request is serviced. The following table shows the internal polling sequence in the same priority level and
the interrupt vector address.
Source
External interrupt 0
Timer 0
External interrupt 1
Timer1
Serial Port 0
Timer2
External interrupt 2
External interrupt 3
SPI
ADC
PCA Counter
Brown-out Detection
Serial Port 1
Keypad Interrupt
Vector address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
Priority within level
1 (highest)
2
3
4
5
6
7
8
9
10
11
12
13
14
The external interrupt nINT0, nINT1, nINT2 and nINT3 can each be either level-activated or transition-activated,
depending on bits IT0 and IT1 in register TCON, IT2 and IT3 in register XICON. The flags that actually generate
these interrupts are bits IE0 and IE1 in TCON, IE2 and IE3 in XICON. When an external interrupt is generated,
the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt
was transition –activated, then the external requesting source is what controls the request flag, rather than the
on-chip hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
The serial port 0 interrupt is generated by the logical OR of RI0 and TI0. Neither of these flags is cleared by
hardware when the service routine is vectored to. The service routine should poll RI0 and TI0 to determine which
one to request service and it will be cleared by software.
The timer2 interrupt is generated by the logical OR of TF2 and EXF2. Just the same as serial port, neither of
these flags is cleared by hardware when the service routine is vectored to.
SPI interrupt is generated by
The ADC interrupt is generated by ADCI in ADCON. It will not be cleared by hardware when the service routine is
vectored to.
46
MG82FEL564 Data Sheet
MEGAWIN