MG82FX564AE Datasheet, PDF (117/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

19.5. External Reset
A reset is accomplished by holding the RESET pin HIGH for at least 24 oscillator periods while the oscillator is
running. To ensure a reliable power-up reset, the hardware reset from RST pin is necessary. After the external
reset completely, hardware sets a flag, EXRF in PCON1, to indicate a external reset happened.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
7
6
5
SWRF
EXRF
BORF
R/W
R/W
R/W
4
IARF
R/W
POR = 0000-XXX0
3
2
--
--
R
R
1
0
--
BOD
R
R/W
Bit 6: EXRF, External Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if an External Reset occurs.
19.6. Brown-Out Reset
In MG82Fx564, if VDD power drops below 4.2V in E series (2.4V in L series), it sets a flag, BOD in PCON1. If
BORE of AUXRA is enabled, BOD event will triggers a RESET to CPU and set a flag, BORF, to indicate a
Brown-Out Reset happened.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
7
6
5
SWRF
EXRF
BORF
R/W
R/W
R/W
4
IARF
R/W
POR = 0000--xxx0
3
2
--
--
R
R
1
0
--
BOD
R
R/W
Bit 5: BORF, Brown-Out Reset Flag.
0: This bit must be cleared by software.
1: Set for the event flag of brown-out reset.
Bit 0: BOD, Brown-Out Detection flag.
0: This bit must be cleared by software.
1: This bit is set if the operating voltage matches the detection level of Brown-Out Detector.
AUXRA: Auxiliary Register A
SFR Address = IFMT
7
6
5
DBOD
BORE
OCDE
R/W
R/W
R/W
POR = 0010--0100
4
3
2
ILRCOE XTALE IHRCOE
R/W
R/W
R/W
1
OSCS1
R/W
0
OSCS0
R/W
Bit 6: BORE, Brown-Out Reset Enable.
0: Disable Reset action if BOD occurs.
1: Enable a Reset action if BOD occurs.
MEGAWIN
MG82FEL564 Data Sheet
117