MG82FX564AE Datasheet, PDF (25/151 Pages) Megawin Technology Co., Ltd – Dual data pointer

6.4. External Data Memory access
AUXR0: Auxiliary Register 0
SFR Page
= All
SFR Address = 0x8E
RESET = 0000-0X0X
7
6
5
4
3
2
1
0
P60OC1 P60OC0 P60FD P34FD MOVXFD ADRJ EXTRAM
--
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit 3: MOVXFD, Fast Driving enabled for MOVX output signals.
0: MOVX output signals with default driving.
1: MOVX output signals with fast driving. If there is an off-chip memory access, MOVX@DPTR or MOVX@Ri, the
MOVX output signals require fast driving for stretched ALE/RD/WR pulse frequency more than 12MHz @5V or
6MHz @3.3V.
Bit 1: EXTRAM, External data RAM enable.
0: Enable on-chip expanded data RAM (XRAM 1024 bytes)
1: Disable on-chip expanded data RAM.
Stretch: MOVX Stretch Register
SFR Page
= All
SFR Address = 0x8F
7
6
5
EMAI1
--
ALES1
R/W
R
R/W
RESET = 0X00-0000
4
3
2
ALES0 RWSH RWS2
R/W
R/W
R/W
1
RWS1
R/W
0
RWS0
R/W
Bit 7: EMAI1, EMAI1 configures the External data Memory Access Interface mode as following:
0: Multiplexed address/data.
1: No Address phase access
Bit 6: Reserved. Software must write ―0‖ on this bit when STRETCH is written.
Bit 5~4: ALES[1:0], EMAI ALE pulse width select bits. It only has effect when EMAI in Multiplexed mode.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycle.
10: ALE high and ALE low pulse width = 3 SYSCLK cycle.
11: ALE high and ALE low pulse width = 4 SYSCLK cycle.
Bit 3: RWSH, EMAI Read/Write pulse Setup/Hold time control.
0: /RD and /WR command Setup/Hold Time = 1 SYSCLK cycle.
1: /RD and /WR command Setup/Hold Time = 2 SYSCLK cycle.
Bit 2~0: RWS[2:0], EMAI Read/Write command pulse width select bits.
000: /RD and /WR pulse width = 1 SYSCLK cycle.
001: /RD and /WR pulse width = 2 SYSCLK cycle.
010: /RD and /WR pulse width = 3 SYSCLK cycle.
011: /RD and /WR pulse width = 4 SYSCLK cycle.
100: /RD and /WR pulse width = 5 SYSCLK cycle.
101: /RD and /WR pulse width = 6 SYSCLK cycle.
110: /RD and /WR pulse width = 7 SYSCLK cycle.
111: /RD and /WR pulse width = 8 SYSCLK cycle.
MEGAWIN
MG82FEL564 Data Sheet
25