MX25L6439E Datasheet, PDF (36/90 Pages) Macronix International – 64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6439E
11-11. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be
issued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 24. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)
CS#
Mode 3
SCLK _{Mode ̌}
Mode Bit Reset
for Quad I/O
̌1 2 3 4 5 6 7
Mode 3
Mode ̌
SIO0
FFh
SIO1
Don’t Care
SIO2
Don’t Care
SIO3
Don’t Care
Figure 25. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)
CS#
Mode 3
SCLK _{Mode ̌}
SIO[3:0]
Mode Bit Reset
for Quad I/O
̌1 2 3 4 5 6 7
FFFFFFFFh
Mode 3
Mode ̌
P/N: PM1842
REV. 1.2, NOV. 06, 2013
36