MX25L6439E Datasheet, PDF (27/90 Pages) Macronix International – 64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6439E
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write En-
able Latch (WEL) bit is reset.
Table 6. Protection Modes
Mode
Software protection
mode (SPM)
Status register condition
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP# and SRWD bit status
Memory
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area cannot
be programmed or erased.
Hardware protection
mode (HPM)
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area cannot
be programmed or erased.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown
in "Table 2. Protected Area Sizes".
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode
(HPM):
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hard-
ware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3,
BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is
entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be en-
tered; only can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O or QPI mode, the feature of HPM will be disabled.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
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