MX25L6439E Datasheet, PDF (35/90 Pages) Macronix International – 64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6439E
Figure 23. 4 x I/O Read enhance performance Mode Sequence (Command EB) (QPI Mode)
CS#
SCLK
MODE 3
MODE 0
SIO[3:0]
CS#
SCLK
MODE 0
SIO[3:0]
01
2
34
56 7
8
9 10 11 12 13 14 15 16 17
EBh
A5 A4 A3 A2
Data In
A1 A0
X XX X
P(7:4) P(3:0)
performance
enhance
indicator
Configurable Dummy cycles
(Note)
H0 L0 H1 L1
MSB LSB MSB LSB
Data Out
n+1 .............
A5 A4 A3 A2 A1 A0
X XX X
6 Address cycles
P(7:4) P(3:0)
performance
enhance
indicator
Configurable Dummy cycles
(Note)
H0 L0 H1 L1
MSB LSB MSB LSB
Data Out
Note: The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM1842
REV. 1.2, NOV. 06, 2013
35