MX25L6439E Datasheet, PDF (33/90 Pages) Macronix International – 64M-BIT [x 1 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6439E
Figure 21. 4 x I/O Read Mode Sequence (Command EB) (QPI Mode)
CS#
SCLK
MODE 3
MODE 0
SIO[3:0]
01
2
34
56 7
8
9 10 11 12 13 14 15 16 17 18 19 20
MODE 3
MODE 0
EB
Data In
A5 A4 A3 A2 A1 A0 X
24-bit Address
(Note)
XX X X
Configurable
Dummy cycle
X H0 L0 H1 L1 H2 L2 H3 L3
MSB
Data Out
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles → data out until CS# goes high → CS# goes low (reduce 4READ instruction) →
24-bit random access address (Please refer to "Figure 22. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)").
In the performance-enhancing mode (Notes of "Figure 22. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And after-
wards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
P/N: PM1842
REV. 1.2, NOV. 06, 2013
33