8408 Datasheet, PDF (9/20 Pages) Maxwell Technologies – Quad 8-Bit Multiplying CMOS D/A Converter with Memory

Quad 8-Bit Multiplying CMOS
D/A Converter with Memory
FIGURE 6. EQUIVALENT DAC CIRCUIT (AII DIGITAL INPUTS LOW)
8408
DIGITAL SECTION
Figure 7 shows the digital input/output structure for one bit. The digital WR, WR, and RD controls shown in the figure
are internally generated from the external A/B, R/W, DS1, and DS2 signals. The combination of these signals decide
which DAC is selected. The digital inputs are CMOS inverters, designed such that TTL input levels (2.4 V and 0.8 V)
are converted into CMOS logic levels. When the digital input is in the region of 1.2 V to 1.8 V, the input stages operate
in their linear region and draw current from the +5 V supply (see Typical Supply Current vs. Logic Level curve on page
6). It is recommended that the digital input voltages be as close to VDD and DGND as is practical in order to minimize
supply currents. This allows maximum savings in power dissipation inherent with CMOS devices. The three-state
readback digital output drivers (in the active mode) provide TTL-compatible digital outputs with a fan-out of one TTL
load. The three state digital readback leakage-current is typically 5 nA.
FIGURE 7. DIGITAL INPUT/OUTPUT STRUCTURE
08.20.02 REV 1
All data sheets are subject to change without notice 9
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