8408 Datasheet, PDF(14/20 Page) Maxwell Technologies – Quad 8-Bit Multiplying CMOS D/A Converter with Memory

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8408 Datasheet, PDF (14/20 Pages) Maxwell Technologies – Quad 8-Bit Multiplying CMOS D/A Converter with Memory

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

APPLICATION HINTS

General Ground Management: AC or transient voltages between AGND and DGND can appear as noise at the 8408âs

analog output. Note that in Figures 5 and 6, IOUT2A/IOUT2B and IOUT 2C/IOUT 2D are connected to AGND. There-

fore, it is recommended that AGND and DGND be tied together at the 8408 socket. In systems where AGND and

DGND are tied together on the backplane, two diodes (1N914 or equivalent) should be connected in inverse parallel

between AGND and DGND.

Write Enable Timing: During the period when both DS and R/W are held low, the DAC latches are transparent and the

analog output responds directly to the digital data input. To prevent unwanted variations of the analog output, the R/W

should not go low until the data bus is fully settled (DATA VALID).

SINGLE SUPPLY, VOLTAGE OUTPUT OPERATION

The 8408 can be connected with a single +5 V supply to produce DAC output voltages from 0 V to +1.5 V. In Figure

10, the 8408 R-2R ladder is inverted from its normal connection. A +1.500 V reference is connected to the current out-

put pin 4 (IOUT 1A), and the normal VREF input pin becomes the DAC output. Instead of a normal current output, the

R-2R ladder outputs a voltage. The OP-490, consisting of four precision low power op amps that can operate its inputs

and outputs to zero volts, buffers the DAC to produce a low impedance output voltage from 0 V to +1.5 V full-scale.

Table 7 shows the code table.

With the supply and reference voltages as shown, better than 1/2 LSB differential and integral nonlinearity can be

expected. To maintain this performance level, the +5 V supply must not drop below 4.75 V. Similarly, the reference

voltage must be no higher than 1.5 V. This is because the CMOS switches require a minimum level of bias in order to

maintain the linearity performance.

TABLE 7. SINGLE SUPPLY BINARY CODE TABLE (REFER TO FIGURE 10)

08.20.02 REV 1

All data sheets are subject to change without notice 14

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