33C408 Datasheet, PDF (9/12 Pages) Maxwell Technologies – 4 Megabit (512K x 8-Bit) CMOS SRAM

4 Megabit (512K x 8-Bit) CMOS SRAM
33C408
WRITE CYCLE NOTE:
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low: A write ends at the earliest transition among CS going high
and WE going high. t_WP is measured from beginning of write to the end of write.
3. t_CW is measured from the later of CS going low to end of write.
4. t_AS is measured from the address valid to the beginning of write.
5. t_WR is measured form the end of write to the address change. TWR applied in case a write ends as CS,
or WR going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary
during read and write cycle.
8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high
impedance state.
9. D_OUT is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading
to the output should not be applied.
04.16.02 REV 8
All data sheets are subject to change without notice 9
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