33C408 Datasheet, PDF (7/12 Pages) Maxwell Technologies – 4 Megabit (512K x 8-Bit) CMOS SRAM

4 Megabit (512K x 8-Bit) CMOS SRAM
33C408
FIGURE 1. AC TEST LOADTIMING WAVEFORM OF READ CYCLE(1)
FIGURE 2. TIMING WAVEFORM OF READ CYCLE (2)
Read Cycle Notes:
1. WE is high for read cycle.
2. All read cycle timing is referenced form the last valid address to the first transition address.
3. t_HZ and t_OHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referenced to V_OH or V_OL levels.
4. At any given temperature and voltage condition, t_HZ(max) is less than t_LZ(min) both for a given device and
from device to device.
5. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100%
tested.
6. Device is continuously selected with CS = V_IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention condition is necessary dur-
ing read and write cycle.
04.16.02 REV 8
All data sheets are subject to change without notice 7
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