DS3105_09 Datasheet, PDF (99/120 Pages) Maxim Integrated Products – Line Card Timing IC

_____________________________________________________________________________________________ DS3105
Register Name:
Register Description:
Register Address:
FSCR3
Frame-Sync Configuration Register 3
7Ch
Bit #
7
6
5
4
3
2
1
0
Name
RECAL
MONLIM[2:0]
SOURCE[3:0]
Default
0
0
1
0
1
0
1
1
Bit 7: Phase Offset Recalibration (RECAL). When set to 1, this configuration bit causes a recalibration of the
phase offset between the output clocks and the selected reference. This process puts the DPLL into mini holdover,
internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the
OFFSET registers, and then switches the DPLL out of mini-holdover. Unlike simply writing the OFFSET registers,
the RECAL process causes no change in the phase offset of the output clocks. RECAL is automatically reset to 0
when recalibration is complete. See Section 7.7.8.
0 = Normal operation
1 = Phase offset recalibration
Bits 6 to 4: External Frame-Sync Monitor Limit (MONLIM[2:0]). When the external frame-sync signal is
misaligned with respect to the MFSYNC output by the specified number of resampling clock cycles, a frame-sync
monitor alarm is declared in the FSMON bit of the OPSTATE register. See Section 7.9.6.
000 =  1UI
001 =  2UI
010 =  3UI
011 =  4UI
100 =  5UI
101 =  6UI
110 =  7UI
111 =  8UI
Bits 3 to 0: External Frame-Sync Reference Source (SOURCE[3:0]). When external frame sync is configured
for SYNC1 automatic mode, this field specifies the input clock to associate with the SYNC1 pin. See Section 7.9.1.
0000–0001 {unused values, undefined}
0011 = IC3
0100 = IC4
0101 = IC5
0110 = IC6
0111–1000 = {unused values, undefined}
1001 = IC9
1010–1011 = {unused value, undefined}
11XX = SYNC123 mode
19-4628; Rev 3; 5/09
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