DS3105_09 Datasheet, PDF (41/120 Pages) Maxim Integrated Products – Line Card Timing IC

_____________________________________________________________________________________________ DS3105
Table 7-18. OC3 Default Frequency Configuration
O3F[2:0] SONSDH
FREQUENCY
(MHz)
O6F[2:0]
=001
OCR2.
OFREQ3
APLL
SRC
000
X
001
0
1
001
0
001
1
010
0
010
1
011*
X
100
X
101
X
110
X
111
X
0
8.192
6.176
8.192
12.352
68.736
22.368
19.44
25.92
38.88
51.84
77.76
*Occurs when O3F[2:0] are left floating.
X
0000
—
FALSE
1101
1101
T4
T4
TRUE
0111
0111
T0
T0
X
1111
T4
X
1110
T4
X
0110
T0
X
0111
T0
X
1000
T0
X
1001
T0
X
1010
T0
7.8.2.5 FSYNC and MFSYNC Configuration
The FSYNC output is enabled by setting FSEN = 1 in the OCR4 register, while the MFSYNC output is enabled by
setting MFSEN = 1 in OCR4. When disabled, these pins are driven low.
When 8KPUL = 0 in FSCR1, FSYNC is configured as an 8kHz clock with 50% duty cycle. When 8KPUL = 1,
FSYNC is an 8kHz frame sync that pulses low once every 125s with pulse width equal to one cycle of output
clock OC3. When 8KINV = 1 in FSCR1, the clock or pulse polarity of FSYNC is inverted.
When 2KPUL = 0 in FSCR1, MFSYNC is configured as an 2kHz clock with 50% duty cycle. When 2KPUL = 1,
MFSYNC is a 2kHz frame sync that pulses low once every 500s with pulse width equal to one cycle of output
clock OC3. When 2KINV = 1 in FSCR1, the clock or pulse polarity f MFSYNC is inverted.
If either 8KPUL = 1 or 2KPUL = 1, output clock OC3 must be generated from the T0 DPLL and must be configured
for a frequency of 1.544MHz or higher or the FSYNC/MFSYNC pulses may not be generated correctly. Figure 7-3
shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits have an
identical effect on MFSYNC.
Figure 7-3. FSYNC 8kHz Options
OC3 OUTPUT CLOCK
FSYNC, 8KPUL=0, 8KINV=0
FSYNC, 8KPUL=0, 8KINV=1
FSYNC, 8KPUL=1, 8KINV=0
FSYNC, 8KPUL=1, 8KINV=1
19-4628; Rev 3; 5/09
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