DS3105_09 Datasheet, PDF (35/120 Pages) Maxim Integrated Products – Line Card Timing IC

_____________________________________________________________________________________________ DS3105
7.8.2.3 OC3 and OC6 Configuration
The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6:
Use Table 7-9 to select a set of output frequencies for each APLL, T0 and T4. Each APLL can only
generate one set of output frequencies. (In SONET/SDH equipment, the T0 APLL is typically
configured for a frequency of 311.04MHz to get N x 19.44MHz output clocks to distribute to
system line cards.)
Determine from Table 7-9 the T0 and T4 APLL frequencies required for the frequency sets chosen
in step 2.
Configure the T0FREQ field in register T0CR1 as shown in Table 7-10 for the T0 APLL frequency
determined in step 3. Configure fields T4CR1:T4FREQ, T0CR1:T4APT0, and T0CR1:T0FT4
as shown in Table 7-12 for the T4 APLL frequency determined in step 3.
Using Table 7-9 and Table 7-13, configure the frequencies of output clocks OC3 and OC6 in the
OFREQn fields of registers OCR2 and OCR4 and the AOFn bits in the OCR5 register.
Table 7-14 lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or
the T4 APLL to obtain each frequency. Table 7-14 also indicates the expected jitter amplitude for each frequency.
Table 7-7. Digital1 Frequencies
DIG1F[1:0]
SETTING IN
MCR7
00
01
10
11
00
01
10
11
DIG1SS
SETTING IN
MCR6
0
0
0
0
1
1
1
1
FREQUENCY
(MHz)
2.048
4.096
8.192
16.384
1.544
3.088
6.176
12.352
JITTER
(pk-pk, ns,
typ)
<1
<1
<1
<1
<1
<1
<1
<1
Table 7-8. Digital2 Frequencies
DIG2AF
SETTING
IN MCR6
1
1
1
1
0
0
0
0
0
0
0
0
DIG2F[1:0]
SETTING
IN MCR7
00
10
00
01
00
01
10
11
00
01
10
11
DIG2SS
SETTING
IN MCR6
0
0
1
1
0
0
0
0
1
1
1
1
FREQUENCY
(MHz)
6.312
10.000
19.440
38.880
2.048
4.096
8.192
16.384
1.544
3.088
6.176
12.352
JITTER
(pk-pk,
ns, typ)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
19-4628; Rev 3; 5/09
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