DS3105_09 Datasheet, PDF (73/120 Pages) Maxim Integrated Products – Line Card Timing IC

_____________________________________________________________________________________________ DS3105
Register Name:
Register Description:
Register Address:
DLIMIT1
DPLL Frequency Limit Register 1
41h
Bit #
7
6
5
4
3
2
1
0
Name
HARDLIM[7:0]
Default
0
1
1
1
0
1
1
0
Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an unsigned integer that specifies the hard frequency limit or pull-in/hold-in range of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL = 1 in the DLIMIT3 register. If the DPLL
frequency exceeds the hard limit the DPLL declares loss-of-lock. The hard frequency limit in ppm is
HARDLIM[9:0]  0.0782. The default value is normally 9.2ppm. If external reference switching mode is enabled
during reset (see Section 7.6.5), the default value is configured to 79.794ppm (3FFh). See Section 7.7.6.
Register Name:
Register Description:
Register Address:
DLIMIT2
DPLL Frequency Limit Register 1
42h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
HARDLIM[9:8]
Default
0
0
0
0
0
0
0
0
Bits 1 and 0: DPLL Hard Frequency Limit (HARDLIM[9:8]). See the DLIMIT1 register description.
19-4628; Rev 3; 5/09
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