MAX1261 Datasheet, PDF (9/20 Pages) Maxim Integrated Products – 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Detailed Description
Converter Operation
The MAX1261/MAX1263 ADCs use a successive-
approximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 12-bit digital output. Their parallel (8 + 4)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1261/MAX1263.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1261
(Figure 3a) and to CH0–CH3 for the MAX1263 (Figure
3b), while IN- is switched to COM (Table 3).
In differential mode, IN+ and IN- are selected from ana-
log input pairs (Table 4) and are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on C_HOLD as a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching C_HOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node 0 to 0V within the
limits of 12-bit resolution. This action is equivalent to
transferring a 12pF[(V_IN+) - (V_IN-)] charge from C_HOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
(CH7)
(CH6)
(CH5)
(CH4)
CH3
CH2
CH1
CH0
COM
CLK
CS
WR
RD
INT
ANALOG
INPUT
MULTIPLEXER
CLOCK
CONTROL LOGIC
AND
LATCHES
( ) ARE FOR MAX1261 ONLY.
REF
REFADJ
17kΩ
A_V =
1.22V
2.05
REFERENCE
T/H
CHARGE REDISTRIBUTION
12-BIT DAC
12
SUCCESSIVE-
APPROXIMATION
REGISTER
COMP
4
8
4
8
MUX
8
8
TRI-STATE, BIDIRECTIONAL
I/O INTERFACE
D0–D7
8-BIT DATA BUS
MAX1261
MAX1263
HBEN
V_DD
V_LOGIC
GND
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1261/MAX1263
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