MAX1261 Datasheet, PDF (10/20 Pages) Maxim Integrated Products – 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
12-BIT CAPACITIVE DAC
REF
INPUT _CHOLD
CH0
MUX _–
+
COMPARATOR
ZERO
CH1
12pF
CH2
R_IN
CH3
C_SWITCH
800Ω
CH4
HOLD
TRACK
CH5
AT THE SAMPLING INSTANT,
CH6
T/H
THE MUX INPUT SWITCHES
CH7
SWITCH
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
COM
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
Figure 3a. MAX1261 Simplified Input Structure
12-BIT CAPACITIVE DAC
REF
CH0
INPUT
MUX
C_HOLD
–+
COMPARATOR
ZERO
12pF
CH1
R_IN
C_SWITCH
800Ω
CH2
HOLD
TRACK
CH3
AT THE SAMPLING INSTANT,
T/H
THE MUX INPUT SWITCHES
SWITCH
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
COM
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1 AND CH2/CH3
Figure 3b. MAX1263 Simplified Input Structure
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V_DD and GND, allow each input channel to
swing within (GND - 300mV) to (V_DD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V_DD + 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/Hold
The MAX1261/MAX1263 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this occurs approximately 1µs after writing the
control byte. In single-ended operation, IN- is connect-
ed to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative (-) input, and the difference of (IN+) - (IN-) is
sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and C_HOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t_ACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
t_ACQ = 9(R_S + R_IN)C_IN
where R_S is the source impedance of the input signal,
R_IN (800Ω) is the input resistance, and C_IN (12pF) is
the ADC’s input capacitance. Source impedances
below 3kΩ have no significant impact on the MAX1261/
MAX1263s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1261/MAX1263 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-alias filtering is recom-
mended.
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1261/MAX1263 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
10 ______________________________________________________________________________________