MAX1261 Datasheet, PDF (8/20 Pages) Maxim Integrated Products – 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
PIN
MAX1261 MAX1263
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
—
16
—
17
—
18
—
19
15
20
16
21
17
22
18
23
19
24
20
25
21
26
22
27
23
28
24
NAME
HBEN
D7
D6
D5
D4
D3/D11
D2/D10
D1/D9
D0/D8
INT
RD
WR
CLK
CS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
COM
GND
REFADJ
REF
V_DD
V_LOGIC
FUNCTION
High Byte Enable. Used to multiplex the 12-bit conversion result:
1: Four MSBs are multiplexed on the data bus.
0: Eight LSBs are available on the data bus.
Tri-State Digital I/O Line (D7)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3, HBEN = 0; D11, HBEN = 1)
Tri-State Digital I/O Line (D2, HBEN = 0; D10, HBEN = 1)
Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
INT goes low when the conversion is complete and the output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on
the data bus.
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In
internal clock mode, connect this pin to either V_DD or GND.
Active-Low Chip Select. When CS is high, digital outputs (D7–D0) are high impedance.
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
0.01µF capacitor. When using an external reference, connect REFADJ to V_DD to disable
the internal bandgap reference.
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to
GND when using the internal reference.
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
Digital Power Supply. V_LOGIC powers the digital outputs of the data converter and can
range from +1.8V to (V_DD + 300mV).
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