MAX1261 Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = V_LOGIC = +2.7V to +3.6V, COM = GND, REFADJ = V_DD, V_REF = +2.5V, 4.7µF capacitor at REF pin, f_CLK = 4.8MHz (50% duty
cycle); T_A = T_MIN to T_MAX unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage
V_DD
2.7
3.6
V
Digital Supply Voltage
Positive Supply Current
V_LOGIC Current
Power-Supply Rejection
V_LOGIC
I_DD
I_LOGIC
PSR
Operating mode,
f_SAMPLE = 250ksps
Standby mode
Internal reference
External reference
Internal reference
External reference
Shutdown mode
C_L = 20pF
f_SAMPLE = 250ksps
Not converting
V_DD = 3V ±10%, full-scale input
1.8
V_DD +
0.3
V
2.3
2.6
1.9
0.9
2.3
1.2
mA
0.5
0.8
2
10
µA
150
µA
2
10
±0.4 ±0.9 mV
TIMING CHARACTERISTICS
(V_DD = V_LOGIC = +2.7V to +3.6V, COM = GND, REFADJ = V_DD, V_REF = +2.5V, 4.7µF capacitor at REF pin, f_CLK = 4.8MHz (50% duty
cycle); T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR
Setup Time
t_CP
t_CH
t_CL
t_DS
t_DH
t_CWS
t_CWH
t_CSWS
208
ns
40
ns
40
ns
40
ns
0
ns
40
ns
40
ns
60
ns
CLK or WR to CS
Hold Time
t_CSWH
0
ns
CS Pulse Width
WR Pulse Width
CS Rise to Output Disable
t_CS
t_WR
(Note 8)
t_TC
C_LOAD = 20pF (Figure 1)
100
ns
60
ns
20
100
ns
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