MAX11208 Datasheet, PDF (9/14 Pages) Maxim Integrated Products – 20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADC with 2-Wire Serial Interface

20-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Detailed Description
The MAX11208 is an ultra-low-power (< 240FA active),
high-resolution, low-speed, serial-output ADC. This
device provides the highest resolution per unit power in
the industry and is optimized for applications that require
very high dynamic range with low power, such as sen-
sors on a 4mA to 20mA industrial control loop.
The MAX11208 provides a high-accuracy internal oscil-
lator, which requires no external components. When
used with the specified data rates, the internal digital
filter provides more than 80dB rejection of 50Hz or 60Hz
line noise. The MAX11208 provides a simple, system-
friendly, 2-wire serial interface in the space-saving,
10-pin FMAX package.
Power-On Reset (POR)
The MAX11208 utilizes power-on reset (POR) supply-
monitoring circuitry on both the digital supply (DVDD)
and the analog supply (AVDD). The POR circuitry
ensures proper device default conditions after either a
digital or analog power-sequencing event.
The MAX11208 performs a self-calibration operation as
part of the startup initialization sequence whenever a
digital POR is triggered. It is important to have a stable
reference voltage available at the REFP and REFN pins
to ensure an accurate calibration cycle. If the reference
voltage is not stable during a POR event, the part should
be calibrated once the reference has stabilized. The part
can be programmed for calibration by using 26 SCLKs
as shown in Figure 3.
The digital POR trigger threshold is approximately 1.2V
and has 100mV of hysteresis. The analog POR trigger
threshold is approximately 1.25V and has 100mV of hys-
teresis. Both POR circuits have lowpass filters that pre-
vent high-frequency supply glitches from triggering the
POR. The analog supply (AVDD) and the digital supply
(DVDD) pins should be bypassed using 0.1FF capaci-
tors placed as close as possible to the package pin.
Analog Inputs
The MAX11208 accepts two analog inputs (AINP and
AINN). The modulator input range is bipolar (-VREF to
+VREF).
Internal Oscillator
The MAX11208 incorporates a highly stable internal
oscillator that provides the system clock. The system
clock runs the internal state machine and is trimmed to
2.4576MHz (MAX11208A) or 2.2528MHz (MAX11208B).
The internal oscillator clock is divided down to run the
digital and analog timing.
Reference
The MAX11208 provides differential inputs REFP and
REFN, for an external reference voltage. Connect the
external reference directly across the REFP and REFN
to obtain the differential reference voltage. The common-
mode voltage range for VREFP and VREFN is between 0
and VAVDD. The differential voltage range for REFP and
REFN is 1V to VAVDD.
Digital Filter
The MAX11208 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC⁴ (sinx/x)⁴ response. When the device is
operating in single-cycle conversion mode, the filter is
reset at the end of the conversion cycle. When operat-
ing in continuous conversion latent mode, the filter is not
reset. The SINC⁴ filter has a -3dB frequency equal to
24% of the data rate.
Serial-Digital Interface
The MAX11208 communicates through a 2-wire serial
interface with a clock input and data output. The output
rate is predetermined based on the package option
(MAX11208A at 120sps and MAX11208B at 13.75sps).
2-Wire Interface
The MAX11208 is compatible with the 2-wire interface
and uses SCLK and RDY/DOUT for serial communica-
tions. In this mode, all controls are implemented by tim-
ing the high or low phase of the SCLK. The 2-wire serial
interface only allows for data to be read out through the
RDY/DOUT output. Supply the serial clock to SCLK to
shift the conversion data out.
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