MAX11208 Datasheet, PDF (11/14 Pages) Maxim Integrated Products – 20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADC with 2-Wire Serial Interface

20-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADC with 2-Wire Serial Interface
SCLK
RDY/DOUT
t5
1
t3
t₁
t2
2
3
D19
D18
CONVERSION IS DONE
DATA IS AVAILABLE
24
t4
0
t7
t6
CONVERSION IS DONE
DATA IS AVAILABLE
Figure 1. Timing Diagram for Data Read After Conversion
SCLK
1
2
3
RDY/DOUT
CONVERSION IS DONE
DATA IS AVAILABLE
D19
D18
24
0
25
25TH SLK RISING EDGE
PULLS RDY/DOUT
HIGH
CONVERSION IS DONE
DATA IS AVAILABLE
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
SCLK
1
2
3
RDY/DOUT
CONVERSION IS DONE
DATA IS AVAILABLE
D19
D18
CALIBRATION STARTS ON 26TH SCLK
24
25
26
25TH SCLK PULLS
RDY/DOUT HIGH
0
1
2
D19 D18
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t8
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
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