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| MAX11135_V1 Datasheet, PDF (9/40 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit,4-/8-/16-Channel ADCs | |||
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MAX11135âMAX11143
500ksps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11141/MAX11142/MAX11143) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 500ksps, fSCLK = 8MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
DYNAMIC PERFORMANCE (250kHz, input sine wave) (Notes 3 and 7)
Signal-to-Noise Plus Distortion
SINAD
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
Full-Power Bandwidth
IMD f1 = 249.878kHz, f2 = 219.97kHz
-3dB
-0.1dB
Full-Linear Bandwidth
SINAD > 49dB
MIN TYP MAX UNITS
49
49.6
dB
49
49.6
dB
-77
-65
dB
63
69
-75
50
7.5
1.5
dB
dB
MHz
MHz
MHz
Crosstalk
-0.5dB below full-scale of 249.878kHz sine-
wave input to the channel being sampled;
apply full-scale 219.97kHz sine wave signal
-88
dB
to all 15 nonselected input channels
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Absolute Input Voltage Range
Static Input Leakage Current
Input Capacitance
tPU
Conversion cycle, external clock
tACQ
312
Internally clocked
fSAMPLE = 500ksps
(Note 8)
5.9
tCONV
Externally clocked, fSCLK = 8MHz, 16
cycles (Note 8)
2000
fSCLK
0.16
8
RMS
30
2 Cycles
ns
µs
ns
8
MHz
ns
ps
VINA
IILA
CAIN
Unipolar (single-ended and pseudo
differential)
Bipolar (Note 9)
RANGE bit set to 0
RANGE bit set to 1
AIN+, AIN- relative to GND
0
-VREF+/2
-VREF+
-0.1
VREF+
V
+VREF+/2
+VREF+
VREF+ +
0.1
V
VAIN_ = VDD, GND
During acquisition time,
RANGE bit = 0 (Note 10)
During acquisition time,
RANGE bit = 1 (Note 10)
-0.1 ±1.5
FA
15
pF
7.5
ââ9
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