MAX11135_V1 Datasheet, PDF (24/40 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit,4-/8-/16-Channel ADCs

MAX11135–MAX11143
500ksps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Averaging Mode
In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
Scan Modes and Unipolar/Bipolar Setting
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes.
Register Descriptions
The MAX11135–MAX11143 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface. Table 1 details the
register access and control. Table 2 through Table 14
detail the various functions and configurations.
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the
ADC operates.
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
Table 1. Register Access and Control
REGISTER NAME
ADC Mode Control
ADC Configuration
Unipolar
Bipolar
RANGE
Custom Scan0
Custom Scan1
SampleSet
Reserved. Do not use.
BIT 15
0
1
1
1
1
1
1
1
1
REGISTER IDENTIFICATION CODE
BIT 14
BIT 13
BIT 12
DIN
DIN
DIN
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
1
1
1
BIT 11
DIN
0
1
0
1
0
1
0
1
DIN ≡ DATA INPUTS
BIT[10:0]
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
Table 2. ADC Mode Control Register
BIT NAME
REG_CNTL
SCAN[3:0]
CHSEL[3:0]
RESET[1:0]
BIT
15
14:11
10:7
6:5
DEFAULT
STATE
0
0001
0000
00
FUNCTION
Set to 0 to select the ADC Mode Control register
ADC Scan Control register (Table 3)
Analog Input Channel Select register (Table 4).
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET1
0
0
1
1
RESET0
0
1
0
1
FUNCTION
No reset
Reset the FIFO only (resets to zero)
Reset all registers to default settings (includes FIFO)
Unused
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