MAX11135_V1 Datasheet, PDF (16/40 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit,4-/8-/16-Channel ADCs

MAX11135–MAX11143
500ksps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Pin Description
MAX11135
MAX11138
MAX11141
(4 CHANNEL)
—
—
26, 27, 28, 1
2–11
—
12
—
13
14, 16
MAX11136
MAX11139
MAX11142
(8 CHANNEL)
—
26, 27, 28, 1–5
—
6–11
—
12
—
13
14, 16
15
15
17, 18
19
17, 18
19
20
20
21
21
22
22
23
23
24
24
25
25
—
—
MAX11137
MAX11140
MAX11143
(16 CHANNEL)
26, 27, 28,
1–11
—
—
—
12
—
13
—
14, 16
15
17, 18
19
20
21
22
23
24
25
—
NAME
FUNCTION
AIN0–AIN13 Analog Inputs
AIN0–AIN7
AIN0–AIN3
GND
CNVST/
AIN14
CNVST
REF-/
AIN15
REF-
GND
REF+
Analog Inputs
Analog Inputs
Ground
Active-Low Conversion Start Input/Analog Input 14
Active-Low Conversion Start Input
External Differential Reference Negative Input /Analog
Input 15
External Differential Reference Negative Input
Ground
External Positive Reference Input. Apply a reference
voltage at REF+. Bypass to GND with a 0.47FF
capacitor.
V_DD
SCLK
CS
DIN
DGND
OVDD
DOUT
EOC
EP
Power-Supply Input. Bypass to GND with a 10FF in
parallel with a 0.1FF capacitors.
Serial Clock Input. Clocks data in and out of the serial
interface
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance or three-state.
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
Digital I/O Ground
Interface Digital Power-Supply Input. Bypass to GND
with a 10FF in parallel with a 0.1FF capacitors.
Serial Data Output. Data is clocked out on the falling
edge of SCLK. When CS is high, DOUT is high
impedance or three-state.
End of Conversion Output. Data is valid after EOC pulls
low (Internal clock mode only).
Exposed Pad. Connect EP directly to GND plane for
guaranteed performance.
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