MAX110 Datasheet, PDF (9/24 Pages) Maxim Integrated Products – Low-Cost, 2-Channel, ±14-Bit Serial ADCs

Low-Cost, 2-Channel, ±14-Bit Serial ADCs
______________________________________________________________Pin Description
PIN
DIP/SO
SSOP
1
1
2
2
3
3
4
6
5
7
NAME
IN1+
REF-
REF+
V_DD
RCSEL
6
8
XCLK
7
9
SCLK
8
10
BUSY
9
11
CS
10
12
DOUT
11
13
DIN
12
16
GND
13
17
V_SS
AGND
14
18
IN2-
15
19
IN2+
16
20
IN1-
—
4, 5, 14, 15
N.C.
FUNCTION
Channel 1 Positive Analog Input
Negative Reference Input
Positive Reference Input
Positive Power-Supply Input—connect to +5V
RC Select Input. Connect to GND to select external clock mode. Connect to V_DD to
select RC OSC mode. XCLK must be connected to V_DD or GND through a resistor
(1MΩ or less) when RC OSC mode is selected.
Clock Input / RC Oscillator Output. TTL/CMOS-compatible oversampling clock input
when RCSEL = GND. Connects to the internal RC oscillator when RCSEL = V_DD. XCLK
must be connected to V_DD or GND through a resistor (1MΩ or less) when RC OSC
mode is selected.
Serial Clock Input. TTL/CMOS-compatible clock input for serial-interface data I/O.
Busy Output. Goes low at conversion start, and returns high at end of conversion.
Chip-Select Input. Pull this input low to perform a control-word-write/data-read opera-
tion. A conversion begins when CS returns high, provided NO-OP is a 1. See the sec-
tion Using the MAX110/MAX111 with SPI, QSPI, and MICROWIRE Serial Interfaces.
Serial Data Output. High-impedance when CS is high.
Serial Data Input. See Control Register section.
Digital Ground
MAX110 Negative Power-Supply Input—connect to -5V
MAX111 Analog Ground
Channel 2 Negative Analog Input
Channel 2 Positive Analog Input
Channel 1 Negative Analog Input
No Connect—there is no internal connection to this pin
_______________Detailed Description
The MAX110/MAX111 ADC converts low-frequency
analog signals to a 16-bit serial digital output (14 data
bits, a sign bit, and an overrange bit) using a first-order
sigma-delta loop (Figure 1). The differential input volt-
age is internally connected to a precision voltage-to-
current converter. The resulting current is integrated
and applied to a comparator. The comparator output
then drives an up/down counter and a 1-bit DAC. When
the DAC output is fed back to the integrator input, the
sigma-delta loop is completed.
During a conversion, the comparator output is a V_REF-
to V_REF+ square wave; its duty cycle is proportional to
the magnitude of the differential input voltage applied
to the ADC. The up/down counter clocks data in from
the comparator at the oversampling clock rate and
averages the pulse-width-modulated (PWM) square
wave to produce the conversion result. A 16-bit static
shift register stores the result at the end of the conver-
sion. Figure 2 shows the ADC waveforms for a differen-
tial analog input equal to 1/2 (V_REF+ - V_REF-). The
resulting comparator and 1-bit DAC outputs are high
for seven cycles and low for three cycles of the over-
sampling clock.
Since the analog input signal is integrated over many
clock cycles, much of the signal and quantization noise
is attenuated. The more clock cycles allowed during
each conversion, the greater the noise attenuation (see
Programming Conversion Time).
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