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| MAX110 Datasheet, PDF (6/24 Pages) Maxim Integrated Products – Low-Cost, 2-Channel, ±14-Bit Serial ADCs | |||
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Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Note 1: These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at VDD = 5V and VSS = -5V (MAX110).
Note 2: 32,768 LSBs cover an input voltage range of ±VREF (15 bits). An additional bit (OFL) is set for VIN > VREF.
Note 3: Guaranteed by design. Not subject to production testing.
Note 4: DNL is less than ±2 counts (LSBs) out of 215 counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5: See 3-Step Calibration section in text.
Note 6: VREF = (VREF+ - VREF-), VIN = (VIN1+ - VIN1-) or (VIN2+ - VIN2-). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7: Conversion time is set by control bits CONV1âCONV4.
Note 8: Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating
Characteristics section for the effect of other clock frequencies. Also read the Clock Frequency section.
Note 9: This current depends strongly on CXCLK (see Applications Information section).
TIMING CHARACTERISTICS (see Figure 6)
(VDD = 5V, VSS = -5V (MAX110), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CS to SCLK Setup Time
(Note 10)
SYMBOL
TA = +25°C
tCSS MAX11_ _C/E
MAX11_ BM
CONDITIONS
MIN TYP
60
80
100
CS to SCLK Hold Time
(Note 10)
tCSH
0
TA = +25°C
60
DIN to SCLK Setup Time
(Note 10)
tDS MAX11_ _C/E
80
MAX11_ BM
100
DIN to SCLK Hold Time
(Note 10)
tDH
0
SCLK, XCLK Pulse Width
(Note 10)
Data Access Time
(Note 10)
SCLK to DOUT Valid
Delay (Note 10)
Bus Relinquish Time
(Note 10)
RC Oscillator Frequency
TA = +25°C
tCK MAX11_ _C/E
MAX11_ BM
tDA CLOAD = 50pF
tDO CLOAD = 50pF
tDH
TA = +25°C
MAX11_ _C/E/M
TA = +25°C
MAX11_ _C/E
MAX11_ BM
TA = +25°C
MAX11_ _C/E
MAX11_ BM
TA = +25°C
MAX11_ _C/E
MAX11_ BM
100
120
160
0
35
0
0
0
60
0
0
35
2.0
1.3
1.1
Note 10: Timing specifications are guaranteed by design. All input control signals are specified with tr = tf = 5ns
(10% to 90% of +5V) and timed from a +1.6V voltage level.
MAX
80
100
120
100
120
140
80
120
2.8
3.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
MHz
6 _______________________________________________________________________________________
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