MAX110 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – Low-Cost, 2-Channel, ±14-Bit Serial ADCs

Low-Cost, 2-Channel, ±14-Bit Serial ADCs
POWER
SUPPLIES
+5V
-5V
GND
POWER
SUPPLIES
+5V
GND
*R = 10Ω
4.7µF
4.7µF
*R = 10Ω
4.7µF
0.1µF
0.1µF
V_DD
GND
V_SS
+5V DGND
MAX110
DIGITAL
CIRCUITRY
0.1µF
V_DD
GND
MAX111
AGND
+5V DGND
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 10a. MAX110 Power-Supply Grounding Connections
A 100ms conversion time cannot be achieved with either
10,240 CCPC or 20,480 CCPC modes because f_OSC
would be below the minimum 250kHz requirement.
When the gain calibration is performed, the conversion
times change approximately 1% to compensate for the
modulator’s gain error. This slightly degrades the line-
frequency rejection, because the corrected conversion
time is no longer an exact multiple of the line frequency.
Typically, the rejection of 50Hz/60Hz from the converter
is 55dB; i.e., if there is 100mV injection at the reference
or the analog input pin, it will cause an uncertainty of
±0.006%. If the system has large 50Hz/60Hz noise, the
use of internal auto gain calibration is not recommend-
ed. Instead, gain calibration should be done off-chip,
using numerical computation methods.
*OPTIONAL
Figure 10b. MAX111 Power-Supply Grounding Connections
If you wish to use a configuration other than those sug-
gested in Table 6, you can accomplish similar 50Hz
and 60Hz line-frequency rejection off-chip by averag-
ing several conversions.
__________Applications Information
Layout, Grounding, Bypassing
For minimal noise, bypass each supply to GND with a
0.1µF capacitor. A ground plane should also be placed
under the analog circuitry. To minimize the coupling
effects of stray capacitance, keep digital lines as far
from analog components and lines as possible. Figure
10 shows the suggested power-supply and ground-
plane connections.
Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz Line
Frequencies
MAX110 (t_CONVERT = 100ms)
81,240 CCPC
102,400 CCPC
DIVIDER
RATIO
f_XCLK
(MHz)
RELATIVE
ACCURACY
(%)
f_XCLK
(MHz)
RELATIVE
ACCURACY
(%)
1:1
0.8124
0.025
1.024
0.065
2:1
1.6248
0.018
2.048
0.045
4:1
3.2496
0.016
4.096
0.030
CCPC = Clock Cycles per Conversion
MAX111 (t_CONVERT = 200ms)
DIVIDER
RATIO
1:1
2:1
4:1
81,240 CCPC
f_XCLK
(MHz)
0.4062
0.8124
1.6248
RELATIVE
ACCURACY
(%)
0.030
0.025
0.022
102,400 CCPC
f_XCLK
(MHz)
0.512
1.024
2.048
RELATIVE
ACCURACY
(%)
0.030
0.025
0.023
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