MAX110 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – Low-Cost, 2-Channel, ±14-Bit Serial ADCs

Low-Cost, 2-Channel, ±14-Bit Serial ADCs
IN1+
DITHER
IN1-
GENERATOR
IN+
INTEGRATOR
IN2+
IN2-
INPUT
MUX
IN-
Gm
Σ
∫
REF+
-
REF-
Gm
MAX110
MAX111
DIN SCLK CS
UP/DOWN
COUNTER
SERIAL
SHIFT
REGISTER
16 16
CONTROL
REGISTER
16 16
TIMER + CONTROL
LOGIC + CLOCK GENERATOR
OSC
DIVIDER
NETWORK,
DIVIDE BY
1, 2, OR 4
RC
OSCILLATOR
DOUT
BUSY
RCSEL
XCLK
Figure 1. Functional Diagram
Oversampling Clock
XCLK internally connects to a clock-frequency divider
network, whose output is the ADC oversampling clock,
f_OSC. This allows the selected clock source (internal RC
oscillator or external clock applied to XCLK) to be
divided by one, two, or four (see Clock Divider-Ratio
Control Bits).
Figure 3 shows the two methods for providing the over-
sampling clock to the MAX110/MAX111. In external-
clock mode (Figure 3a), the internal RC oscillator is
disabled and XCLK accepts a TTL/CMOS-level clock to
provide the oversampling clock to the ADC.
Select external-clock mode (Figure 3a) by connecting
RCSEL to GND and a TTL/CMOS-compatible clock to
XCLK (see Selecting the Oversampling Clock
Frequency).
In RC-oscillator mode (Figure 3b), the internal RC oscil-
lator is active and its output is connected to XCLK
(Figure 1). Select RC-oscillator mode by connecting
RCSEL to V_DD. This enables the internal oscillator and
connects it to XCLK for use by the ADC and external
system components. Minimize the capacitive loading on
XCLK when using the internal RC oscillator.
V_REF+
DIFFERENTIAL
ANALOG
INPUT
DC LEVEL AT 1/2 V_REF
V_REF-
V_REF+
OUTPUT FROM
1-BIT DAC
V_REF-
OVERSAMPLING
CLOCK
Figure 2. ADC Waveforms During a Conversion
MAX110
MAX111
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