MAX1036 Datasheet, PDF (9/22 Pages) Maxim Integrated Products – 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
A. F/S-MODE I²C SERIAL INTERFACE TIMING
SDA
tSU.DAT
tLOW
SCL
tHD.STA
S
tHIGH
tR
tF
B. HS-MODE I²C SERIAL INTERFACE TIMING
tHD.DAT
SDA
tSU.DAT
tLOW
tHD.DAT
SCL
tHD.STA
S
tHIGH
tRCL
tFCL
tSU.STA
tHD.STA
Sr
A
tSU.STA
tHD.STA
Sr
A
HS-MODE
tR
tF t
tBUF
tSU.STO
P
tRDA
S
tFDA
tBUF
tSU.STO
tRCL1
S
F/S-MODE
Figure 1. I²C Serial Interface Timing
of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or series of conversions are
then internally clocked (eight clock cycles per conver-
sion) and the MAX1036–MAX1039 hold SCL low. When
operating in external clock mode, the T/H circuitry
enters track mode on the seventh falling edge of a valid
slave address byte. Hold mode is then entered on the
falling edge of the eighth clock cycle. The conversion is
performed during the next eight clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
between conversions. The acquisition time (t_ACQ) is the
minimum time needed for the signal to be acquired. It
is calculated by:
t_ACQ ≥ 6.25 ✕ (R_SOURCE + R_IN) ✕ C_IN
where R_SOURCE is the analog input source impedance,
R_IN = 2.5kΩ, and C_IN = 18pF. t_ACQ is 1/f_SCL for external
V_DD
I_OL = 3mA
SDA
V_OUT
400pF
I_OH = 0mA
Figure 2. Load Circuit
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select R_SOURCE,
allow 625ns for t_ACQ in internal clock mode to account
for clock frequency variations.
_______________________________________________________________________________________ 9