MAX1036 Datasheet, PDF (14/22 Pages) Maxim Integrated Products – 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. 1-BYTE WRITE CYCLE
1
7
11
8
11
S
SLAVE ADDRESS
WA
SETUP OR
CONFIGURATION BYTE
A P OR Sr
NUMBER OF BITS
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. 2-BYTE WRITE CYCLE
1
7
11
8
1
8
11
S
SLAVE ADDRESS
WA
SETUP OR
CONFIGURATION BYTE
A
SETUP OR
CONFIGURATION BYTE
A P OR Sr
NUMBER OF BITS
Figure 9. Write Cycle
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
in random access memory (RAM). If the scan mode is
set for multiple conversions, they all happen in succes-
sion with each additional result being stored in RAM.
The MAX1036/MAX1037 contain 8 bytes of RAM, and
the MAX1038/MAX1039 contain 12 bytes of RAM. Once
all conversions are complete, the MAX1036–MAX1039
release SCL, allowing it to be pulled high. The master
can now clock the results out of the output shift register
at a clock rate of up to 1.7MHz. SCL is stretched for a
maximum acquisition and conversion time of 7.6µs per
channel (Figure 10).
The device RAM contains all of the conversion results
when the MAX1036–MAX1039 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. RAM contents can be read contin-
uously. If reading continues past the last result stored in
RAM, the pointer wraps around and points to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the master
(typically a microcontroller) from the burden of running
the conversion clock.
External Clock
When configured for external clock mode (CLK = 1),
the MAX1036–MAX1039 use SCL as the conversion
clock. In external clock mode, the MAX1036–MAX1039
begin tracking the analog input on the seventh falling
clock edge of a valid slave address byte. One SCL
clock cycle later, the analog signal is acquired and the
conversion begins. Unlike internal clock mode, convert-
ed data is available immediately after the slave-address
acknowledge bit. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to readdress the
device with a read command to obtain new conversion
results (Figure 11).
The conversion must complete in 9ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 1ms.
The MAX1036–MAX1039 must operate in external clock
mode for conversion rates up to 188ksps.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded
from a multichannel scan.
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