MAX1036 Datasheet, PDF (5/22 Pages) Maxim Integrated Products – 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 2.7V to 3.6V (MAX1037/MAX1039), V_DD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, V_REF = 2.048V
(MAX1037/MAX1039), V_REF = 4.096V (MAX1036/MAX1038). External clock, f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless otherwise
noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
Setup Time for a Repeated START
Condition (Sr)
t_SU, _STA
CONDITIONS
MIN TYP MAX UNITS
160
ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
t_HD, _DAT (Note 12)
t_SU, _DAT
t_RCL (Note 13)
0
150
ns
10
ns
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
t_RCL1 (Note 13)
20
160
ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t_FCL
t_RDA
t_FDA
t_SU, _STO
C_B
t_SP
(Note 13)
(Note 13)
(Note 13)
20
80
ns
20
160
ns
20
160
ns
160
ns
400
pF
0
10
ns
Note 1: The MAX1036/MAX1038 are tested at V_DD = 5V and the MAX1037/MAX1039 are tested at V_DD = 3V. All devices are config-
ured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground ON channel; sine wave applied to all OFF channels.
Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V_DD.
Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV_P-P.
Note 10: Electrical characteristics are guaranteed from V_DD(min) to V_DD(max). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11: Power-supply rejection ratio is measured as:
[ ] ^VFS^{(3.3V) − V}FS^(2.7V)
×
2^N
V_REF
3.3V − 2.7V
, for the MAX1037/MAX1039 where N is the number of bits (8) and V_REF = 2.048V.
Power-supply rejection ratio is measured as:
[ ] ^VFS^{(5.5V) − V}FS^(4.5V)
×
2^N
V_REF
5.5V − 4.5V
, for the MAX1036/MAX1038 where N is the number of bits (8) and V_REF = 2.048V.
Note 12: A master device must provide a data hold time for SDA (referred to V_IL of SCL) in order to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: C_B = total capacitance of one bus line in pF. t_R and t_F measured between 0.3V_DD and 0.7V_DD. Minimum specification is
tested at +25°C with C_B = 400pF.
Note 14: f_SCLH must meet the minimum clock low time plus the rise/fall times.
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