MAX1036 Datasheet, PDF (8/22 Pages) Maxim Integrated Products – 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
PIN
MAX1036/
MAX1037
1, 2, 3
—
—
MAX1038/
MAX1039
8, 7, 6
5, 4, 3, 2, 1
16, 15, 14
4
—
—
13
5
9
6
10
7
11
8
12
Pin Description
NAME
FUNCTION
AIN0–AIN2
AIN3–AIN7
AIN8–AIN10
AIN3/REF
AIN11/REF
SCL
SDA
GND
V_DD
Analog Inputs
Analog Input 3/Reference Input or Output. Selected in the setup
register.
Analog Input 11/Reference Input or Output. Selected in the setup
register.
Clock Input
Data Input/Output
Ground
Positive Supply. Bypass to GND with a 0.1µF capacitor.
Detailed Description
The MAX1036–MAX1039 ADCs use successive-
approximation conversion techniques and input T/H cir-
cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX1036/MAX1037 are
4-channel ADCs, and the MAX1038/MAX1039 are 12-
channel ADCs. These devices feature a high-speed 2-
wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional dia-
gram for the MAX1038/MAX1039.
Power Supply
The MAX1036–MAX1039 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX1037/MAX1039 feature a 2.048V internal
reference and the MAX1036/MAX1038 feature a 4.096V
internal reference. All devices can be configured for
use with an external reference from 1V to V_DD.
Analog Input and Track/Hold
The MAX1036–MAX1039 analog input architecture con-
tains an analog input multiplexer (MUX), a T/H capaci-
tor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer con-
nects C_T/H to the analog input selected by CS[3:0] (see
the Configuration/Setup Bytes (Write Cycle) section). The
charge on C_T/H is referenced to GND when converted. In
pseudo-differential mode, the analog input multiplexer
connects C_T/H to the ‘+’ analog input selected by
CS[3:0]. The charge on C_T/H is referenced to the ‘-’ ana-
log input when converted.
The MAX1036–MAX1039 input configuration is pseudo-
differential in that only the signal at the ‘+’ analog input
is sampled with the T/H circuitry. The ‘-’ analog input
signal must remain stable within ±0.5LSB (±0.1LSB for
best results) with respect to GND during a conversion.
To accomplish this, connect a 0.1µF capacitor from ‘-’
analog input to GND. See the Single-Ended/Pseudo-
Differential Input section.
During the acquisition interval, the T/H switches are in
the track position and C_T/H charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C_T/H as a sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva-
lent to transferring a charge of 18pF ✕ (V_IN+ - V_IN-)
from C_T/H to the binary weighted capacitive DAC form-
ing a digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge
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