DS1371 Datasheet, PDF (9/14 Pages) Maxim Integrated Products – 2-Wire, 32-Bit Binary Counter Watchdog Clock

DS1371
Time-of-Day Counter
The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the
address range 00h–03h. When the counter is read, the current time of day is latched into a register, which
is output on the serial data line while the counter continues to increment. Writing to the counter resets the
countdown chain for the time-of-day counter (Figure 2). The watchdog countdown chain is unaffected. If
the square-wave output is enabled and is set to 1Hz, the output resets when the countdown chain is reset.
Because the other square-wave frequencies are derived before the section of the countdown chain that is
reset, the other frequencies are unaffected by a write to the time-of-day counter.
Watchdog/Alarm Counter
The watchdog/alarm counter is a 24-bit down counter. The contents can be read or written by accessing
the address range 04h–06h. When this counter is written, both the counter and a seed register are loaded
with the written value. The countdown chain for the watchdog counter is reset when the counter is
written. The time-of-day countdown chain is unaffected. When the counter is to be reloaded, it uses the
value in the seed register. In alarm mode, when the counter is read, the current counter value is latched
into a register, which is output on the serial data line while the counter continues to decrement. In
watchdog mode, reading any of the watchdog registers reloads the seed value.
If the counter is not needed, it can be disabled and used as a 24-bit cache of general-purpose RAM by
setting the WACE bit in the control register to logic 0. If all 24 bits of the watchdog/alarm counter are
written to a 0 when WACE = 1, the counter is disabled and the AF bit is not set.
When the WD/ALM bit in the control register is set to a logic 0, the WD/ALM counter decrements every
second, until it reaches 0. At this point, the AF bit in the status register is set, the counter is reloaded, and
restarted.
When the WD/ALM bit is set to a logic 1, the WD/ALM counter decrements every 1/4096 of a second
(approximately every 244µs) until it reaches 0, sets the AF bit in the status register, and stops. If AIE = 1
and INTCN = 1, the SQW/INT pin pulses low for 250ms. The pulse cannot be truncated by writing either
AF or AIE to a 0 during the low time of the SQW/INT pin. At the end of the 250ms pulse, the AF bit is
cleared to a 0 and the SQW/INT pin becomes high impedance. The WD/ALM counter can be reloaded and
restarted before the counter reaches 0 by:
1) Reading or writing any of the WD/ALM counter registers (WDS must be low).
2) A low-to-high transition on the WDS pin.
Note: WDS must be low when configuring the watchdog.
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